JPS639708B2 - - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION The present invention relates to a signal transmitting/receiving device for time-division bidirectional communication on a two-wire transmission path using digital signals, and in particular, the present invention relates to a signal transmitting/receiving device in which the signal processing speed within the device and the signal transmission speed of the transmission path are mutually controlled. Concerning a buffer circuit that converts .

As one means of bidirectional information transmission, there is a time-division bidirectional transmission method in which transmission and reception are performed alternately using a two-wire line. Since this method changes the transmission direction over time, the signal transmission speed of the transmission line needs to be more than twice the speed required for unidirectional transmission, that is, the signal processing speed within the device. Therefore, since the signal processing speed within the device and the signal transmission speed of the transmission line are different, a buffer circuit for speed conversion is provided to perform bidirectional transmission between the two devices by half-duplex communication.

FIG. 1 is a block diagram of an example of memory use of a conventional buffer circuit. In FIG. 1, 10 is a signal transmission/reception source such as a terminal device or a switching center;
21 is a memory having the same number of addresses as the number of transmission signal bits of the transmission line; 30 is a transmission line interface circuit; 40 is a two-wire transmission line; 50 is a control circuit;
Counters 1 and 53 operate at the signal transmission speed of the transmission path, and counters 52 and 54 operate at the signal processing speed within the device. A method of using the memory of the buffer circuit will be explained using the timing chart shown in FIG. As an example, the signal processing speed on the equipment side
64 kb/s, and the signal transmission speed of the transmission line is 144 kb/s. When receiving from the transmission line, the 144 kb/s received signal from the transmission line 40 is waveform-shaped in the line interface circuit 30, and the signal transmission speed of the transmission line is 144 kHz. is written (R ₀ ) into the memory 20 between time t ₀₀ and t ₁₀ within the unit period P ₀ of the transmission line signal block. Then speed 60k
By addressing according to the Hz counter 52, the time
A continuous signal (R ₀ ') of 64 kb/s is read from the memory 20 from t ₁₀ to t ₁₁ within the next unit period P ₁ .
and sends the signal to the terminal device 10.

Furthermore, when transmitting to the transmission path, the 64 kb/s transmission signal from the terminal device 10 is sent from time t ₂₀ to time t ₂₁ by addressing according to the counter 54 at a speed of 64 kHz.
write to memory 21 during (S ₁ ), then speed
With addressing according to 144kHz counter 53,
The signal is read from the memory 21 between time t ₂₁ and time t ₃₁ to create a 144 kb/s signal (S ₁ '), and the signal is sent to the transmission line interface circuit 30. By repeating these operations every cycle P ₀ , P ₁ , P _{2 .} . . , a burst signal block (R ₀ , R ₁ , R _{2 .} . . S ₀ ′, S ₁ ′, S ₂ ′…) and continuous signals (R ₀ ′, R ₁ ′, R ₂ ′…S ₀ ,
S ₁ , S _{2 .} . . ) and speed conversion is performed. protection time
TG prevents interference between transmitted data and received data on a two-wire transmission path, and corresponds to a time width of several bits of a 144 kb/s signal.

However, in the time period when writing and reading are performed simultaneously for one memory, that is, for the memory 20, the times t ₀₁ to _{t 11} (R ₁ and R ₀ '), t ₀₂ to _{t 12} (R ₂ and
R ₁ ′), etc., for the memory 21, from time t ₂₀ to t ₃₀
(S ₀ ′ and S ₁ ), t ₂₁ to t ₃₁ (S ₁ ′ and S ₂ ), etc., so a special memory called elastic memory is required. Furthermore, regarding the address counter, since the maximum number of addresses in the memory is the same as the number of signal bits in the transmission line, four counters 51 to 54 with different counter starting points are required, making the peripheral control circuitry complex. There was a drawback.

The present invention aims to improve these drawbacks by eliminating the overlap of read and write operations for the memory and simplifying the peripheral control circuits including the reduction of the counter circuit. Its characteristics are:
Two memories with the number of addresses more than twice the number of transmission signal bits on the transmission line, one counter that operates at the transmission speed of the transmission line, and one counter that operates at the data processing speed of the device are provided, and the transmission Within one unit cycle time of a path signal block, one memory is used for writing and reading transmission and reception signals on the transmission path side, and the other memory is used for writing and reading transmission and reception signals on the device side. Then, within one unit cycle time of the next transmission line signal block, the writing and reading operations of the transmitting and receiving signals in the two memories are exchanged between the device side and the transmission line side, thereby configuring a buffer circuit. .

Hereinafter, embodiments of the present invention will be described in detail with reference to the drawings.

FIG. 3 is a block diagram of one embodiment of the present invention. In FIG. 3, 70 and 71 are memories with addresses that are more than twice the number of transmission signal bits on the transmission line, 60 is a control circuit, 61 is a counter that operates at the signal transmission speed of the transmission line, and 62 is an internal memory in the device. It is a counter that operates at signal processing speed. other number 10,
30 and 40 are equivalent to the same numbers in FIG.

The operation of FIG. 3 will be explained using the timing chart of FIG. 4. Similar to the explanation of the conventional example in FIG. 2, in the embodiment of the present invention, the signal processing speed on the device side
64kb/s, and the signal transmission speed of the transmission line is 144kb/s, when receiving from the transmission line, transmission line 4
The 144kb/s received signal from 0 is waveform-shaped in the line interface circuit 30, and the speed is 144kHz.
The data is written to the upper half address of the memory 70 between time t ₀₀ and t ₁₀ within the period P ₀ of the transmission line signal block by addressing according to the counter 61 of the transmission line signal block. (4th
Figure a-R ₁ ) Then, within the next cycle P ₁ , the contents of the upper address of the memory 70 are read at a speed according to the counter 62 of 64 kHz (Figure 4 a-R ₁ ').
It is sent to the terminal device 10 as a 64 kb/s signal. At this time, the transmission/reception signal from the transmission path in cycle P ₁ is written to the upper half address of the other memory 71 with address designation according to count 61 (Fig. 4b-R ₂ ), and in the next cycle P ₂ , the corresponding The contents of the upper address of the memory 71 are read according to the count 62 (FIG. 4 b-R ₂ ') and sent to the terminal device 10 as a 64 kb/s signal. Below, the switching use of these two memories will be explained using the transmission path signal block period (P ₀ , P ₁ , P ₂ ...).
Accordingly, by performing this on the transmission line side and the equipment side, from the 144kb/s signal (R ₁ , R ₂ , R ₃ ...)
Speed conversion to 64 kb/s signals (R ₁ ', R ₂ ', R ₃ '...) is performed (Fig. 4 c, d).

On the other hand, when transmitting to the transmission path, the 64 kb/s transmission signal from the terminal device 10 is sent to the lower part of the memory 71 at times t ₀₀ to _{t 40} within the period P ₀ by addressing according to the counter 62 with a speed of 64 kHz. Write to half the address (Fig. 4b-S ₁ ), then write to the next cycle
Between time t ₂₁ and t ₃₁ of P ₁ , the contents of the lower address of the memory are read out by addressing according to the counter 61 at a speed of 144 kHz and sent to the transmission line interface circuit 30 (Fig. 4b-S ₁ ').

Also, the terminal device 10 in the period P ₁ at this time
The transmitted signal is written to the address in the lower half of the other memory 70 according to the counter 62 at a speed of 64 kHz (FIG. 4a-S ₂ ), and then written from time t ₂₂ to t ₃₂ of the next cycle P ₂ . In the meantime, the contents of the lower address of the memory 70 are read out according to the counter 61 at a rate of 144 kHz and sent to the line interface circuit 30 (FIG. 4a-S ₂ ').

Hereinafter, the switching use of these two memories will be explained according to the period of the transmission line signal block (P ₀ , P ₁ , P ₂ . . . ).
By performing this on the transmission line side and the equipment side,
Perform speed conversion from 64kb/s signals (S ₁ , S ₂ , S ₃ ...) to 144kb/s signals (S ₁ ', S ₂ ', S ₃ '...) (Fig. 4 c, d), protection Regarding the time width of time TG,
This is equivalent to the conventional example shown in FIG.

Here, the reason why R ₂ and S ₁ ′ and R ₃ and S ₂ ′ can write and read memory according to the same address counter 61 is because the number of addresses of the used memories 70 and 71 is the same as that of the transmission line. This is because there are more than twice the number of signal bits, and in the embodiment of the present invention, as an example of double the number, R ₂ and R ₃ are made to correspond to upper addresses, and S ₁ ′ and S ₂ ′ are made to correspond to lower addresses. .

As explained above, the present invention is a method for switching the use of memory constituting a buffer circuit for speed conversion when the signal processing speed in the device and the signal transmission speed on the transmission path are different, such as elastic memory. This has the advantage that the speed conversion circuit can be constructed using ordinary memory and a minimum number of counters without using any special memory.

[Brief explanation of the drawing]

FIG. 1 is a block diagram of a conventional buffer circuit, FIG. 2 is a timing diagram for explaining the operation of FIG. 1, and FIG. 3 is a block diagram of an embodiment of the present invention.
FIG. 4 is a timing diagram for explaining the operation of FIG. 3. DESCRIPTION OF SYMBOLS 10... Signal receiving source such as a terminal device or switching center, 20, 21... Memory having the same number of addresses as the number of transmission signal bits of the transmission line, 30... Transmission line interface circuit, 40... Two-wire transmission line, 50,
60... Control circuit, 51, 53, 61... Counter that operates at the signal transmission speed of the transmission path, 52, 54, 6
2...A counter that operates at the signal processing speed within the device;
70, 71...Memories having twice the number of addresses as the number of transmission signal bits on the transmission line.

Claims (1)

[Scope of Claims] 1. A buffer circuit for speed conversion provided when the signal processing speed within the device and the signal transmission speed of the transmission path are different, comprising: a counter that operates at the signal processing speed within the device;
A counter that operates at the signal transmission speed of the transmission line and two memories with addresses that are more than twice as many as the transmission signal bits on the transmission line are provided, and one memory is is used for writing and reading transmission and reception signals on the transmission line side, and the other memory is used for writing and reading transmission and reception signals on the device side, and within the unit cycle time of the immediately next consecutive transmission line signal block, the two memories are A memory switching method for a buffer circuit, characterized in that a buffer circuit for speed conversion of signals is configured by continuously exchanging writing and reading operations of transmitted and received signals between the device side and the transmission line side.