KR920001859B1 - Time switch control memory device - Google Patents

Abstract

The apparatus is to control maximum four time switch memory apparatus (TSMA) and to interchange data for testing time switch control memory apparatus (TCMA) with a time switch processor (TSP). The apparatus includes an interfacing unit (1) for interfacing the TSP and the TSMA, a shift register (2) for converting serial MOD/ADDR signal into parallel, a decoder (3) for decoding four mode bits to discriminate TSP functions, a circuit pack inspecting circuit for checking a circuit pack, a TSMA interfacing unit (5) for interchanging data with the TSMA, a latch unit (9) for latching 16 bit data transmitted from a shift register (8), a control memory unit (10) for reading and writing data needed to control the TSMA, a timing controller (6) for generating internal reference clock signal and latch clock signal, and a parity checker (11) for checking the parity code of the 16 bit data.

Description

Time switch control memory device

1 is a block diagram of the present invention.

2 is a control data format diagram of the control memory unit.

Figure 3 shows the parallelized ADDR format.

* Explanation of symbols for main parts of the drawings

1: processor interface circuit 2: shift register

3: mode decoding circuit 4: circuit pack confirmation circuit

5: TSMA interface circuit 6: Timing control circuit

7: counter 8: shift register

9: Latch Circuit 10: Control Memory

11, 14: parity check circuit 12, 13: latch circuit

The present invention relates to a time switch control memory device for use in an electronic switch.

One of the basic configurations in the digital exchange system is a time switch device that performs time slot exchange (TSI). The basic function of the time switch is to exchange all timeslots on the Incomming Highway with any time slots on the Outgoing Highway.

Such a time switch device to which the present invention is applied includes a time switch call memory device (referred to as TSMA), a data link interface device (referred to as DLIA), a test and maintenance device (referred to as TTMA), and a multiplex / demultiplex device. (Called MDXA).

An object of the present invention is to control up to four TSMAs from a processor (hereinafter referred to as a TSP) that controls a time switch device to receive control data for performing a time slot exchange function of the TSMA in the time switch device. The present invention provides a position control memory device (hereinafter referred to as TCMA) and a device for exchanging related data for testing the TSMA with the TSP. Hereinafter, the present invention will be described in detail with reference to the accompanying drawings. 1 is a block diagram showing the configuration of the present invention. The processor interface circuit 1 functions to interface with the TSP. The TD bus, which is an interface path with the TSP, is redundant to improve reliability, and the transmission method uses the RS-485 method. The TD buses that are duplicated into this device are selected by the TB-SEL signals in each TD bus and exchange the following signals with the TSP through the TD buses.

-CSK: Shifter Clock from TSP

-FS: Generated when transferring data from TSP

-TxD: Data from TSP (1 byte)

-RxD: Data to TSP (1 byte)

-MODx / ADDRx: Execution mode and TCMA from TSP, control memory and talk memory address point and circuit pack selection bit in TSMA

-RDY: Occurs when data transmission starts with TSP

-TB-SEL: Select TD Bus from TSP

The MOD / ADDR (0-3) signals from the TSP are each parallelized by four shift registers 2, and the mode decoding circuit 3 decodes the four mode bits by the decoding circuit to determine the function to be performed. Decode and each corresponding execution mode is shown in the following table.

TABLE 1

The mode decoding circuit 3 is implemented using two 71LS138IC chips. Also, the parallelized ADDR format is shown in FIG. The function of each bit of the ADDR format diagram is as follows.

2, 3, 4, 6, 7, 8, 11, 12, 15, and 16 of FIG. 3 designate an address pointer of a control memory or a currency memory, 1 distinguishes a write or read execution mode, and 5 represents It specifies which group control memory of two groups of control memory to control. 10, 13, 14 are used to select the corresponding TCMA among the number of TCMAs in this time switch device, and 9 is the number of accesses.

As already mentioned, there are several TCMAs in the time switch device, and the TSP processes the plain bits, the direction bits, and the TCMA confirmation bits (10, 13, 14 in Fig. 3) to select the TCMAs to control. After performing the TCMA circuit pack check by the circuit pack confirmation circuit 4 with the bits parallelized by the shift register 2 through the interface circuit 1, the RDY signal is transmitted to the TSP in the selected TCMA.

When the TSP executes the control data write mode to the control memory of the TCMA, the TSP sets the execution mode to the control memory write mode, fixes the corresponding MOD bit, selects the corresponding ADDR bit with the control memory corresponding memory address pointer, and then selects the TCMA selection bits. When the RDY signal is sent to the TSP from the TCMA selected by the circuit pack confirmation circuit 4, the TSP parallelizes the TXD via the TD bus. Since TSP accesses by byte (8 bits), two accesses must be performed for the device to perform normal operation. At this time, the number of access strokes is represented by bit 9 of FIG. The latch circuit 9 latches the 16-bit data that has been accessed twice to provide the input data of the control memory section 10, and the parity check 11 connected to the latch circuit 9 is the 16-bit received from the TSP. The parity signal of the data is monitored, and when an error occurs, a fault signal is sent to the TCMA. The parity check 11 is implemented using 74F280, 74LS74, 74LS123 IC chip and its peripheral circuit.

The control memory unit 10 stores control data for controlling the call memory device in the TSMA, and in one embodiment of the present invention, the minimum of the control memory capacity to control the call memory of the TSMA performing 1024 timeslot exchanges. The unit was (1K x 16) bits. However, when the TSMA's timeslot exchange capacity is expanded to 2048 timeslots, another control memory group (1K × 16) can be included in the TCMA, where bit 5 of FIG. 3 is selected to select the control memory to be controlled by the TSP. Will be used. On the other hand, the control data in the control memory unit 10 is composed of a 10-bit call memory read address for reading 1024 addresses of the call memory device, a TSMM select 2 bit for controlling up to four TSMAs, and a parity bit. It consists of a dual-port CMOS SRAM. 2 is a control data format diagram of the control memory unit 10. As shown in FIG.

The data in the control memory section 10 are sequentially read by the counter 7 output in 122 ns cycles and are randomly written by the TSP (RWSR: Random Write Sequential Read). The latch circuit 139 functions to latch data from the control memory section 10 to the 8192 KHz clock outputted from the timing control circuit 6 and transmit the data to the TSMA, where the parity check 14 is read from the control memory. When an error is detected and a parity signal of the bit data is detected, a fault signal is sent to the TTMA which collects the fault signal.The timing control circuit 6 inputs the control clocks CP3, FP3, and CP3D necessary for the present invention. Each part provides a latch clock and a basic clock of the counter 7. Here, the CP3 clock is 8192KHz, the FP3 clock is 8KHz, and the CP3D clock is 8192KHz delayed 90 degrees from the CP3 clock. 74F04 and 74L74 were used.

In the control data read mode, the TSP reads data of an arbitrary address of the control memory unit 10 and performs the check and other maintenance functions of the control memory unit 10. The latch circuit 12 is connected to the control memory section 10 so that the control memory output data is latched by a latch clock coming out of the circuit pack confirming circuit 4 at the request of the TSP and parallel / serial by the shift register 8. And is transferred to the TSP through the processor interface circuit 1. The memory initialization circuit 15 initializes all address data values in the control memory to "1" when the power supply in this apparatus is "ON".

In general, when a memory having a common input and output is used for the control memory unit 10, a memory having a fast access time of 30 ns or more must be used to process data at 8.912 Mbps, and the overall system clock is a fast clock of 16 MHz or more. This is a demand. In the present invention, only a write operation is performed through the left port and a read operation is performed using the right port by using a memory having a dual port. However, when this unit's power is turned `` ON '' for memory initialization, the write mode is performed through the right port for 250μs, or two frames (one frame interval is 125μs). In this way, by using a memory with dual ports to separate writes and reads, if a memory with a relatively slow access time (70ns) can be used, the overall system clock uses 8.192MHz, which improves the reliability of the device. . In case of using dual-port memory, address conflict occurs when accessing the same address at the same time at the same time. As a solution, the write operation is performed for twice the time interval of the read operation on the right port. Do it. By performing an internal timeslot write operation during two timeslots, at least one timeslot writes normally, and this is not a problem even if the read operation on the right port is rejected due to an address conflict. The control memory unit 10 is implemented using four IDT7130LA70P IC chips.

One TCMA controls up to four TSMAs, so that the TSP needs to test whether it is normal or need to receive data at a specific address in a call memory, or write specific data at a specific address. Send and receive related data through When the TSP writes specific data to a specific address of the communication memory in TSMA, it selects the relevant mode according to Table 1 and sends it to TCMA, which is decoded by the mode decoding circuit (3) and sent to TSMA through the TSMA interface circuit (5). When the acknowledgment (ACK) signal from the selected TSMA is received by the TCMA through the TSMA interface circuit 5, it is sent back to the circuit pack confirmation circuit 4 to make an RDY signal and sent to the TSP. The RxD received from the TSP is parallelized by the shift register and sent to the TSMA through the TSMA interface circuit 5. Further, when the TSP wants to read a specific address in a specific TSMA among the TSMAs, the same operation described above is repeated to transfer the 16-bit parallel data received from the TSMA through the TSMA interface circuit 5 to the shift register 8. By parallel / serial conversion to TSP. The present invention is configured as described above and receives control data for performing the time slot exchange function of the TSMA from the time switch processor (TSP) to control up to four TSMA, the TSP and related data for testing the TSMA and Interchange.

Claims (4)

An apparatus for exchanging a time switch control process (TSP) and related data within a time switch device and controlling a talk memory device (TSMA), comprising: a processor interface circuit connected to the TSP and having a redundant TD bus (1) ), A shift register 2 connected to the processor interface circuit 1 for serial / parallel conversion of a MOD / ADDR signal, and four shift registers connected to the shift register 2 to determine a function to be performed by a TSP. A circuit pack confirmation circuit connected to the mode decoding circuit 3 for decoding mode bits, the shift register 2 and the mode decoding circuit 3, and the processor interface circuit 1 to perform circuit pack verification by control bits ( 4) a TSMA interface circuit connected to the shift register 2 and the mode decoding circuit 3 and the circuit pack checking circuit 4 for exchanging related data with the TSMA. (5), a bidirectional serial / parallel conversion and a parallel / serial conversion shift register 8 connected to the processor interface circuit 1 and the TSMA interface circuit 5 for exchanging 8-bit data with a TSP, and the shift register ( 8) and a latch circuit 9 for latching 16-bit data paralleled by a shift register, and connected to the shift register 2 and a latch circuit 9, connected to a circuit pack check circuit 4 to connect the TSMA. Control memory means (10) for storing and sequentially reading data necessary for control, a timing control circuit (6) for receiving basic clocks from the outside to provide an internal basic clock and other necessary latch clocks, said timing control circuit (6) and a counter (7) connected to the control memory means (10) to provide a sequential read address of the control memory means (10), and connected to the latch circuit (9) from a TSP. A parity check circuit 11 for monitoring the new 16-bit parity, a latch circuit 13 connected to the control memory means 10 for sending a call memory diary address and control bits to TSMA, and the control memory means 10 A parity check circuit 14 for monitoring parity of control memory output data, and a control memory output data connected to the control memory means 10 from the circuit pack checking circuit 4 at the request of a TSP. And a latch circuit (12) which is latched by a latch clock coming out and output to the shift register (8). 2. The time switch according to claim 1, further comprising a memory initialization circuit (15) connected to said control memory means (10) for initializing data of the control memory means when the power of the apparatus is " ON ". Control memory device. 2. The time switch control memory device according to claim 1, wherein said control memory means (10) comprises four dual-port CMOS SRAMs. 4. The time switch control memory according to claim 3, wherein the write operation is performed during two time intervals of the read operation of the right port during the write operation through the left port to solve the address conflict problem of the dual port memory. Device.

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