JP2734627B2 - Bus master device - Google Patents

Description

Description: TECHNICAL FIELD The present invention relates to an arithmetic and control unit and a bus master device including a plurality of slave devices connected to the arithmetic and control unit via a bus. The reliability of information transmission in a bus master device, in which addresses and data are multiplexed from a device such as a microprocessor which outputs the data via separate buses and transmitted to a slave device via a multiplex bus Regarding improvement.

<Prior Art> FIG. 10 is a conceptual diagram showing an example of a conventional bus master device.

In the figure, 1 is a bus master device, and 21 and 22 are a plurality of bus slave devices connected to the bus master device 1 via a bus BS. The bus BS includes a data line and a parity bit line, and the side receiving the data checks the parity bits transmitted through the parity bit line to determine whether or not the transmitted data is error-free. And secures the reliability of information transmission.

FIG. 11 is a conceptual diagram showing the configuration of still another example of the conventional bus master device. In this example, the bus master device 1 and each of the slave devices 21 to 2n are connected via a bus BS including only data lines. In this device,
Since there are a plurality of slave devices, it is not advantageous in terms of cost to make each slave device check the parity bit. Therefore, in this device, the master device 1 outputs certain data, and the data is read back and checked by the master device 1 to improve reliability.

<Problems to be Solved by the Invention> By the way, in order to realize the bus master device having the configuration shown in FIG. 11 which does not add the parity bit and maintain the reliability with a simple configuration, it is necessary to use a recent ASIC. It is necessary to use a method that matches the tendency of In other words, the scale of the logic that can be configured inside is rapidly increasing, so that other logic circuits except for microprocessors, memories, bus drivers, etc. can be made ASICs as much as possible, thus greatly reducing the cost. It becomes possible.

In this case, increasing the number of input / output PINs of the ASIC is not desirable from the viewpoint of package cost and mounting.

The present invention has been made in view of such a point, and in a bus configuration system in which the number of bus slave devices is larger than the number of bus master devices, the reliability of information transmission in the bus master device is ensured. It is an object of the present invention to provide an apparatus which can convert a part of the function for performing ASIC to an ASIC.

<Means for Solving the Problems> FIG. 1 is a block diagram showing a basic configuration of a bus master device of the present invention. In the figure, BM is a bus master device, BS is a multiplex bus (E bus) for multiplexing and transmitting addresses and data, and is accessed by the bus master device BM. Bus master device
In the BM, reference numeral 1 denotes a microprocessor which transfers an address or data to an internal address bus AB or an internal data bus DB.
And a data output unit 11 for outputting the data.

21 and 22 are buffers provided on the internal address bus AB, 3
Reference numerals 1 and 32 denote buffers provided in the internal data bus DB, each of which switches each bus and functions as a driver. Reference numeral 4 denotes an ASIC block that receives various control signals C-CTL from the microprocessor 1 and
Control means 41 for controlling the buffers 21, 22, 31, and 32, and comparison means 42 for inputting data on the internal address bus AB and data on the internal data bus DB and comparing the two data. .

<Operation> For example, an address is output from the data output means of the microprocessor 1 onto the multiplex bus BS via the internal address bus AB, for example, and address data on the multiplex bus BS is received via the internal data bus DB,
The comparing means 42 compares the data on the address bus with the data on the returned data bus, and if they do not match, detects a clamping failure of the multiplex bus.

<Example> Hereinafter, an example of the present invention will be described in detail with reference to the drawings.

FIG. 2 is a configuration block diagram showing an embodiment of the present invention. In the figure, the same components as those in FIG. 1 are denoted by the same reference numerals.

A multiplex bus (E bus) BS is connected to a plurality of slave devices (not shown), and a bus master device.
The BM accesses this and transmits addresses and data in a time-division manner. Also, the bus from the control means 41
One control signal line (E-CTL) is included. The control signal line here exchanges control signals of the asynchronous confirmation system, and transmits the following five signals.

EWRITE: Indicates that access to the E bus BS is a write sequence.

AS: Address strobe ATK: Address transfer acknowledgment DS: Data strobe DTK: Data transfer acknowledgment The microprocessor 1 transfers an address to the internal address bus AB via the CA bus and a CD bus. And outputs data to the internal data bus DB, respectively.
And the following 4 using the control signal line (C-CTL).
Exchange of two signals.

WRITE: Indicates that the access is a write sequence ST: Strobe TK: Transfer acknowledgment ERR: Signal indicating that a clamp failure has been detected by accessing the E bus In the ASIC conversion block 4, reference numeral 44 denotes an internal address bus AB
The address decoder decodes the above data, and if the result is addressed to the E bus BS, asserts the output SEL signal and transmits it to the control means 41. The address decoder 45 transmits the data on the internal address bus AB to the control means 43 from the control means 43. This is a register that latches when the latch signal LT rises, and the data latched here is output to the internal data bus DB via the buffer 46.

The operation of the device configured as described above is described as follows. When a clamp is detected when a read cycle is normal, when a read cycle (write cycle) address is read back, a clamp is detected when a write cycle is normal and when data is read back in a write cycle. Each case will be described separately.

(When the read cycle is normal) FIG. 3 is a time chart showing the operation in this state, FIG. 7 is a state transition diagram of the control means 41 in FIG. 2, and FIG.
The figure is an explanatory diagram of this state transition diagram.

The control means 41 enables the buffer 21 by asserting the control signal E1 when the bus cycle of the microprocessor 1 starts, and outputs an address from the microprocessor 1 to the internal address bus AB (state 1). In this state, the decoder 44 decodes the address output to the internal address bus AB, knows that it is an address to the E bus, and outputs a signal SEL indicating this to the control means 4.
Apply to 1.

The control means 41 receives this signal SEL and shifts to state 2.
Assert the control signals E4, E5, E6, LT respectively, and
5 latch the address information on the internal address bus AB,
This is output to the E bus BS via the buffer 46, the internal data bus DB, and the buffer 32, respectively, and is read back via the buffer 22 internal address bus AB. Comparison means 24
Compares the output of the register 45 with the address information read back via the internal address bus AB, and if both information match, determines that the address read back is normal, and then moves to state 3. In this state, the address strobe AS, ATK, data strobe DS
Are asserted, read access to the E bus is performed, and the state moves to the state R4.

In this state, the buffer 32 is disabled and a state of waiting for read data from the slave device is set. When read data is returned from the bus slave device, status R5
Move on to

In the state R5, the control signal LT is asserted to
Then, the read data returned from the bus slave device via the internal address bus AB is latched. Control signal at the same time
Assert E3, E4 and drive buffers 31b, 46 to drive CD
The latch data of the register 45 is applied to the microprocessor 1 via the bus, and the read cycle is completed.
When the read cycle of the microprocessor 1 ends,
The control means 41 returns to the state 1 again. When the bus cycle ends, the slave device pulls up the read data and returns to the initial state.

(When Clamp is Detected at Read Cycle (Write Cycle) Address Readback) FIG. 4 is a time chart showing the operation in this case. The operations up to state 1 and state 2 by the control means 41 are as follows:
This is performed in the same manner as in FIG.

Here, in state 2, as a result of comparing and comparing the output of the register 45 and the address information read back via the internal address bus AB, the comparing means 42 detects a mismatch between the two information. As a result, it is determined that the address readback is abnormal, and the clamp signal CLMP is output from the comparing means 42 to the control means 41.
Is applied to When receiving the clamp signal CLMP, the control means 41 shifts to the state E, outputs an error signal ERR indicating this to the microprocessor 1, and returns to the state 1.

FIG. 5 is a time chart showing the operation in this case. The operations up to state 1, state 2, and state 3 by the control means 41 are performed in the same manner as in FIG. 3, except that write data is output from the microprocessor 1 to the CD bus.

In the state W4, the control means 41 outputs the control signals E2 and E6 to drive the buffers 31a and 32, and outputs the write data on the CD bus of the microprocessor 1 to the E bus BS. At the same time, the buffer 22 is driven to read back the write data, and the comparing means 42 compares the data on the internal address bus AB with the data on the internal data bus DB.

Based on the comparison result, it is determined whether the write data read back is abnormal or normal. If determined to be normal, move to state W5,
Here, a data strobe DS is sent to the slave device, a data transfer acknowledgment DTK from the slave device is waited, and upon receipt of the data strobe DS, a transition is made to state W6, where a signal TK indicating the sequence end is output to the microprocessor 1. Then, the write cycle ends.

When the write cycle of the microprocessor 1 is completed, the control means 41 returns to the state 1.

FIG. 6 is a time chart showing the operation in this case (when a clamp is detected at the time of reading back data in a write cycle). State 1, State 2, State 3, State by control means 41
The operation up to W4 is performed in the same manner as in FIG. In state W4, when the comparison means 42 detects an error in reading back the write data, the comparison means 42 outputs a clamp signal CLMP, and the control means 41 receives this and shifts to state E. In the state E, an error signal ERR is output to the microprocessor 1 and the state returns to the state 1.

FIG. 9 is a block diagram of a main part showing another embodiment of the present invention.

In this embodiment, the buffers 22 and 32 are inserted into the respective buses so that the directions are opposite.

In this embodiment, output to the E bus (multiplex bus) is performed from the internal address bus AB, and reading back is performed via the internal data bus DB.

<Effects of the Invention> As described above in detail, according to the present invention, data on the internal data bus or the internal address bus is output on the multiplex bus, and this data is output via the internal address bus or the internal data bus. By reading back and comparing both data, a clamp failure of the multiplex bus or a failure of the data output buffer can be detected without adding a parity bit, and the reliability of the system can be improved with a simple configuration.

Further, since the internal address bus and the internal data bus are used in a time-division manner and the data on each bus is input to detect the failure, the circuit for the failure detection can be easily formed into an ASIC.

In addition, there is an effect that the inspection can be performed every time in each cycle of address output and data output.

[Brief description of the drawings]

FIG. 1 is a block diagram showing a basic configuration of a bus master device of the present invention, FIG. 2 is a block diagram showing a configuration of an embodiment of the present invention, and FIG. FIG. 4 is a time chart showing an operation, FIG. 4 is a time chart showing an operation when a clamp is detected at the time of reading back a read cycle (write cycle) address in the apparatus of FIG. 2, and FIG. 5 is a write cycle normal in the apparatus of FIG. FIG. 6 is a time chart showing an operation when a clamp is detected at the time of reading back data in a write cycle in the apparatus of FIG. 2, and FIG. 7 is a state of control means in the apparatus of FIG. FIG. 8 is a descriptive explanatory diagram of this state transition diagram, FIG. 9 is a block diagram of a main part showing another embodiment of the present invention, and FIG. 10 is a conventional bus master. Configuration conceptual diagram illustrating an example of a device, the
FIG. 11 is a conceptual diagram showing the configuration of still another example of the conventional bus master device. BM: Bus master device BS: Multiplex bus 1: Microprocessor 11: Data output means 21, 22, 31, 32: Buffer 4: ASIC block 41: Control means, 42: Comparison means

Claims (1)

(57) [Claims] A bus master device for multiplexing an address and data from a device for outputting an address and data via separate buses and transmitting the multiplexed address and data to a slave device via a multiplex bus. Means for outputting data on an internal data bus or an internal address bus from the device to a multiplex bus; and outputting an address from the device to a multiplex bus via the internal address bus. A read-back means for reading back via an empty internal bus and outputting data from the device to a multiplex bus via an internal data bus from the device via the currently available internal bus; Address or data and read back means And a comparing means for comparing the observed return address information or data, bus master device and detecting the clamping failure of multiplexed bus by the output of the comparison means.