JPH0441394Y2 - - Google Patents

Description

[Detailed Description of the Invention] <Industrial Application Field> The present invention is directed to a central processing unit connected to a motherboard bus including an address bus and a data bus, and a main memory accessed by this central processing unit. The present invention relates to an information processing device consisting of a device, and is particularly equipped with a failure detection function for a motherboard bus.

<Prior Art> Regarding an information processing device consisting of a central processing unit and a main memory connected to a motherboard bus including an address bus and a data bus, the address bus and data bus are connected to other signals and power supplies. If the internal transmitter or receiver fails, this information processing device will not be able to detect the above failure, and may write incorrect data.
A situation occurred in which a read was performed or an incorrect address was accessed.

Another method is to set parity bits on the address bus and data bus and use these parity bits to detect failures on the motherboard bus, but in this case too, if there is a failure of two or more bits on the bus. I was unable to detect this when it occurred.

<Problem to be solved by the invention> The problem to be solved by the invention is to strengthen the fault detection function on the motherboard bus, and to improve the reliability of data transfer on the motherboard bus. The purpose is to increase

<Means for solving the problem> The present invention, which solves the above problems, uses an address bus that includes an address bus and a data bus to specify whether the current bus cycle is a normal bus cycle or a self-diagnosis bus cycle. Mother with a modification line
board bus and the contents of the address bus in the self-diagnostic bus cycle.
a main memory device provided with a selector that outputs to the bus; and a comparator that outputs diagnostic information in the self-diagnosis bus cycle and compares whether the contents of the address bus and the data bus match. This is an information processing device equipped with a central processing unit provided with.

<Function> In the information processing device of the present invention, the central processing unit transmits a self-diagnosis mode signal, which causes the central processing unit to output diagnostic information onto the address bus, while the main storage device outputs the address bus by the selector. The diagnostic information given from the bus is output to the data bus, and the central processing unit
Compare the data on the bus and if they do not match, it is considered a motherboard bus failure.

<Example> The figure shows an example of an information processing device implementing the present invention.

In this figure, 10 is the central processing unit CPU;
20 is a main storage device, which is interconnected by a motherboard bus 30.

Here, the motherboard bus 30 has an address bus B, a data bus DB, and a CPU
Address modification line AM driven by 10
has.

In addition to its own internal CPU functions 11, the CPU 10 has a comparator 12 that compares the address information output on the address bus AB with the data information on the data bus DB.

The main memory device 20 has a unique main memory internal function 21
In addition, it has a selector 22 that switches between address information given from address bus AB and data information output to data bus DB.

The operation of the information processing apparatus of the present invention configured as described above will be explained separately in (1) normal mode and (2) self-diagnosis mode. Note that the self-diagnosis mode is activated at regular intervals in the normal mode.

(1) Normal mode The CPU 10 outputs a normal bus cycle signal to the address modification line AM, and
By outputting an address to AB, data is accessed from main memory 20 via data bus DB.

(2) Self-diagnosis mode The CPU 10 outputs a self-diagnosis bus cycle signal to the address modification line AM. In response to this signal, the internal function 11 of the CPU sends an address signal (self-diagnosis information) to the address bus that is incremented by "1" every time a self-diagnosis bus cycle is performed.
Output to AB.

On the other hand, in the main storage device 20, the selector 22 is driven, and the self-diagnosis information given from the address bus AB is switched to data from the internal function 21 and output on the data bus DB. Respond to access.

Next, when the CPU 10 receives the response from the main storage device 20 side, the comparator 12 compares the data on the data bus DB with the self-diagnosis information sent from the internal function 21 .

If both information matches, the CPU
10 assumes that the motherboard bus 30 is normal, shifts to normal mode, and performs normal operations.

If they do not match, it is assumed that the motherboard bus 30 has failed, and abnormality processing is activated.

As described above, according to the present invention, it is possible to shorten the signals of the address bus and data bus on the motherboard bus, and to control the transmission and reception parts of the address bus and data bus with respect to the motherboard bus. All failures can be detected.

<Effects of the invention> In the information processing device of the invention, the central processing unit transmits a self-diagnosis mode signal, which causes the central processing unit to output diagnostic information onto the address bus, while the main memory is controlled by the selector. The diagnostic information given from the address bus is output to the data bus, and the central processing unit outputs the diagnostic information and data transmitted from within.
If the data on the bus does not match, it is considered a motherboard bus failure, which strengthens the failure detection function on the motherboard bus. The reliability of data transfer can be increased.

[Brief explanation of the drawing]

The figure is a diagram showing the configuration of an information processing device according to the present invention. 10...Central processing unit CPU, 11...CPU internal functions, 12...Comparator, 20...Main storage device,
21...Main memory internal function, 22...Selector, 30
...Mother board bus, AB...Address
Bus, DB...data bus, AM...address modification line.

Claims (1)

[Scope of utility model registration request] A motherboard bus that includes an address bus and a data bus and is provided with an address modification line that specifies whether the current bus cycle is a normal bus cycle or a self-diagnosis bus cycle; a main memory device provided with a selector for outputting the contents of the address bus to the data bus; and a main memory device provided with a selector for outputting the contents of the address bus to the data bus; An information processing device comprising a central processing unit provided with a comparator for comparing whether or not they match.