JPS6382969U - - Google Patents
Info
- Publication number
- JPS6382969U JPS6382969U JP17757786U JP17757786U JPS6382969U JP S6382969 U JPS6382969 U JP S6382969U JP 17757786 U JP17757786 U JP 17757786U JP 17757786 U JP17757786 U JP 17757786U JP S6382969 U JPS6382969 U JP S6382969U
- Authority
- JP
- Japan
- Prior art keywords
- printed circuit
- circuit board
- pattern
- chip
- board
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Pending
Links
- 239000000853 adhesive Substances 0.000 claims description 4
- 230000001070 adhesive effect Effects 0.000 claims description 4
- 239000000758 substrate Substances 0.000 claims 1
- 238000010586 diagram Methods 0.000 description 2
- 238000000034 method Methods 0.000 description 1
- 238000005476 soldering Methods 0.000 description 1
Landscapes
- Electric Connection Of Electric Components To Printed Circuits (AREA)
Description
第１図は本考案のチツプ実装用プリント基板の
一実施例の平面図、第２図は第１図の要部拡大図
、第３図はチツプ部品の代表例であるチツプ抵抗
器の斜視図、第４図ａ〜ｃはチツプ実装基板への
チツプの実装工程を説明する説明図、第５図ａは
チツプ部品取付用パターンランドに適切に接着剤
が塗布された状態を示す説明図、第５図ｂ，ｃは
チツプ部品取付用パターンランドに不適切に接着
剤が塗布された状態を示す説明図、第６図は半田
付け不良状態のチツプ実装基板上のチツプ部品の
断面図である。
１……チツプ抵抗器、２……チツプ実装基板、
２ａ……主基板、２ｂ……副基板、２ｄ……パタ
ーンランド、２ｅ……基準穴、３……接着剤、５
……パターンランド。
Fig. 1 is a plan view of an embodiment of the printed circuit board for chip mounting of the present invention, Fig. 2 is an enlarged view of the main part of Fig. 1, and Fig. 3 is a perspective view of a chip resistor, which is a typical example of a chip component. , FIGS. 4a to 4c are explanatory diagrams illustrating the process of mounting a chip onto a chip mounting board, FIG. 5b and 5c are explanatory diagrams showing a state in which adhesive has been inappropriately applied to the pattern lands for mounting chip components, and FIG. 6 is a sectional view of a chip component on a chip mounting board with poor soldering. 1... Chip resistor, 2... Chip mounting board,
2a...Main board, 2b...Subboard, 2d...Pattern land, 2e...Reference hole, 3...Adhesive, 5
...Pattern Land.
Claims (1)
リント基板の、チツプ部品実装側の面の回路パタ
ーンに関係のない空き領域に、チツプ部品仮止め
用の接着剤の塗布間隔と同じ間隔でパターンラン
ドを形成したことを特徴とするチツプ実装用プリ
ント基板。 ２ 前記プリント基板が実際にチツプ部品および
他の電子部品を実装する主プリント基板と、この
主プリント基板に切り離し可能に連続する回路パ
ターンのない副基板とを備えており、前記パター
ンランドを前記副基板に形成したことを特徴とす
る実用新案登録請求の範囲第１項に記載のチツプ
実装用プリント基板。 ３ 前記パターンランドが複数組あり、それぞれ
の組のパターンランドは前記接着剤の塗布量に応
じた異なる径となつていることを特徴とする実用
新案登録請求の範囲第１項または第２項に記載の
チツプ実装用プリント基板。[Scope of Claim for Utility Model Registration] 1. Application of adhesive for temporarily fixing chip components to an empty area unrelated to the circuit pattern on the side where chip components are mounted on a printed circuit board on which chip components and other electronic components are mounted. A printed circuit board for chip mounting, characterized in that pattern lands are formed at the same intervals as the spacing. 2. The printed circuit board includes a main printed circuit board on which chip components and other electronic components are actually mounted, and a sub-board without a circuit pattern that is detachably continuous with the main printed board, and the pattern land is connected to the sub-board. A printed circuit board for chip mounting according to claim 1, characterized in that the printed circuit board is formed on a substrate. 3. According to claim 1 or 2 of the utility model registration claim, there are a plurality of sets of pattern lands, and each set of pattern lands has a different diameter depending on the amount of adhesive applied. Printed circuit board for chip mounting as described.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP17757786U JPS6382969U (en) | 1986-11-20 | 1986-11-20 |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP17757786U JPS6382969U (en) | 1986-11-20 | 1986-11-20 |
Publications (1)
| Publication Number | Publication Date |
|---|---|
| JPS6382969U true JPS6382969U (en) | 1988-05-31 |
Family
ID=31118906
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP17757786U Pending JPS6382969U (en) | 1986-11-20 | 1986-11-20 |
Country Status (1)
| Country | Link |
|---|---|
| JP (1) | JPS6382969U (en) |
-
1986
- 1986-11-20 JP JP17757786U patent/JPS6382969U/ja active Pending