JPS6365330U

JPS6365330U -

Info

Publication number: JPS6365330U
Application number: JP16055186U
Authority: JP
Priority date: 1986-10-20
Filing date: 1986-10-20
Publication date: 1988-04-30

Description

[Brief explanation of the drawing]

第１図は本考案の実用例図、第２図は本考案で
あるＡ／Ｄ変換装置を用いたレーダ信号処理装置
の一例図、第３図は、従来からある直並列型Ａ／
Ｄコンバータの一例である１２ビツト直並列Ａ／
Ｄ変換器のブロツク図、第４図は直並列Ａ／Ｄ変
換器における誤差検出回路の入出力波形の一例図
であり、図中、１はアンテナ、２は受信機、３は
本考案であるＡ／Ｄ変換装置、４はレーダ信号処
理装置、５ａ，５ｂは６ビツトＡ／Ｄコンバータ
、６はＤ／Ａコンバータ、７は誤差検出回路、８
はレジスタ、９はサンプルホールダ、１０はタイ
ミング発生回路、１１はアナログデイレイであり
、イは外部クロツク信号、ロはアナログ入力信号
、ハはアナログデイレイ出力信号、ニはＤ／Ａコ
ンバータ出力、ホは誤差検出回路の出力信号、ヘ
は下位６ビツトＡ／Ｄコンバータの出力信号、ト
はレジスタ出力信号、チはサンプルホールダ制御
信号である。なお、図中同一あるいは相当部分に
は同一符号を付して示してある。 Fig. 1 is a diagram of a practical example of the present invention, Fig. 2 is an example of a radar signal processing device using the A/D converter of the present invention, and Fig. 3 is a diagram of a conventional serial-parallel type A/D converter.
A 12-bit series/parallel A/D converter is an example of a D converter.
The block diagram of the D converter, FIG. 4, is an example of the input and output waveforms of the error detection circuit in the series-parallel A/D converter. In the figure, 1 is the antenna, 2 is the receiver, and 3 is the present invention. A/D conversion device, 4 is a radar signal processing device, 5a, 5b are 6-bit A/D converters, 6 is a D/A converter, 7 is an error detection circuit, 8
is a register, 9 is a sample holder, 10 is a timing generation circuit, 11 is an analog delay, A is an external clock signal, B is an analog input signal, C is an analog delay output signal, D is a D/A converter output, and H is an analog delay output signal. The output signal of the error detection circuit, F is the output signal of the lower 6-bit A/D converter, G is the register output signal, and H is the sample holder control signal. It should be noted that the same or corresponding parts in the drawings are designated by the same reference numerals.

Claims

[Scope of utility model registration request]

two parallel A/D converters for the upper and lower parallel A/D converters; a D/A converter that converts the output of the upper parallel A/D converter into an analog signal; an analog delay that adjusts the timing of the analog input signal; Analog delay output and the D
an error detection circuit that detects the difference between /A converter outputs;
Consisting of a lower parallel A/D converter that converts the output of the error detection circuit into a digital signal, a register that adjusts the timing of the output of the upper parallel A/D converter, and a timing generation circuit that controls the timing of each component. Series-parallel type A
An A/D converter, characterized in that the A/D conversion frequency is made variable by using a sample holder in place of the analog delay.