JPH01171368U - - Google Patents
Info
- Publication number
- JPH01171368U JPH01171368U JP6771688U JP6771688U JPH01171368U JP H01171368 U JPH01171368 U JP H01171368U JP 6771688 U JP6771688 U JP 6771688U JP 6771688 U JP6771688 U JP 6771688U JP H01171368 U JPH01171368 U JP H01171368U
- Authority
- JP
- Japan
- Prior art keywords
- circuit
- peak
- output signals
- holding circuit
- balanced
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Pending
Links
- 238000001514 detection method Methods 0.000 claims description 4
- 238000006243 chemical reaction Methods 0.000 claims description 3
- 239000003990 capacitor Substances 0.000 claims 1
- 238000007599 discharging Methods 0.000 claims 1
- 238000010586 diagram Methods 0.000 description 3
Landscapes
- Measurement Of Current Or Voltage (AREA)
Description
第１図はこの考案の一実施例によるピーク検出
回路のブロツク図、第２図はこの考案の一実施例
によるピーク検出回路の回路図、第３図は第１図
における不平衡―平衡変換回路の入力信号と出力
信号の波形図、第４図は従来のピーク検出回路の
回路図である。
１は入力端子、２は不平衡―平衡変換回路、３
はピーク保持回路、４は比較回路、５は選択回路
、６は出力端子。なお、図中、同一符号は同一、
または相当部分を示す。
Fig. 1 is a block diagram of a peak detection circuit according to an embodiment of this invention, Fig. 2 is a circuit diagram of a peak detection circuit according to an embodiment of this invention, and Fig. 3 is an unbalanced-balanced conversion circuit in Fig. 1. FIG. 4 is a circuit diagram of a conventional peak detection circuit. 1 is an input terminal, 2 is an unbalanced-balanced conversion circuit, 3
is a peak holding circuit, 4 is a comparison circuit, 5 is a selection circuit, and 6 is an output terminal. In addition, in the figure, the same reference numerals are the same,
or a significant portion.
Claims (1)
に変換する不平衡―平衡変換回路と、コンデンサ
の充放電により前記の２つの平衡出力信号のピー
ク値を保持するピーク保持回路と、このピーク保
持回路で保持された２つのピーク値を比較する比
較回路と、この比較回路の比較の結果に従つて前
記ピーク保持回路で保持された２つのピーク値の
どちらか一方を出力する選択回路とを備えたピー
ク検出回路。 An unbalanced-balanced conversion circuit that converts an input signal into balanced output signals of the same phase and inverted phase, a peak holding circuit that holds the peak values of the two balanced output signals by charging and discharging a capacitor, and this peak holding circuit. and a selection circuit that outputs either one of the two peak values held by the peak holding circuit according to the comparison result of the comparison circuit. Peak detection circuit.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP6771688U JPH01171368U (en) | 1988-05-23 | 1988-05-23 |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP6771688U JPH01171368U (en) | 1988-05-23 | 1988-05-23 |
Publications (1)
| Publication Number | Publication Date |
|---|---|
| JPH01171368U true JPH01171368U (en) | 1989-12-05 |
Family
ID=31293075
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP6771688U Pending JPH01171368U (en) | 1988-05-23 | 1988-05-23 |
Country Status (1)
| Country | Link |
|---|---|
| JP (1) | JPH01171368U (en) |
-
1988
- 1988-05-23 JP JP6771688U patent/JPH01171368U/ja active Pending