JPS6361828U - - Google Patents
Info
- Publication number
- JPS6361828U JPS6361828U JP15504786U JP15504786U JPS6361828U JP S6361828 U JPS6361828 U JP S6361828U JP 15504786 U JP15504786 U JP 15504786U JP 15504786 U JP15504786 U JP 15504786U JP S6361828 U JPS6361828 U JP S6361828U
- Authority
- JP
- Japan
- Prior art keywords
- digital converter
- analog
- parallel
- series
- converter
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Pending
Links
- 238000010586 diagram Methods 0.000 description 5
- 238000006243 chemical reaction Methods 0.000 description 4
- 238000001514 detection method Methods 0.000 description 2
- 238000000034 method Methods 0.000 description 1
Landscapes
- Analogue/Digital Conversion (AREA)
Description
第１図はこの考案の一実施例を示すＡ／Ｄ変換
装置のブロツク図、第２図はＡ／Ｄ変換装置を用
いたレーダ信号処理装置を示す図、第３図は従来
からあるＡ／Ｄ変換方式の一例である１２ビツト
直並列Ａ／Ｄ変換器のブロツク図、第４図は直並
列Ａ／Ｄ変換器における誤差検出回路の入出力信
号波形図である。
図中１はアンテナ、２は受信機、３はＡ／Ｄ変
換装置、４はレーダ信号処理装置、５ａ，５ｂは
６ビツトＡ／Ｄコンバータ、６はスイツチ、７は
Ｄ／Ａコンバータ、８はアナログデイレイ、９は
誤差検出回路、１０はレジスタである。なお図中
同一あるいは相当部分には同一符号を付して示し
てある。
Fig. 1 is a block diagram of an A/D conversion device showing an embodiment of this invention, Fig. 2 is a diagram showing a radar signal processing device using the A/D conversion device, and Fig. 3 is a diagram showing a conventional A/D conversion device. FIG. 4 is a block diagram of a 12-bit series-parallel A/D converter which is an example of the D conversion method, and is a diagram of input/output signal waveforms of an error detection circuit in the series-parallel A/D converter. In the figure, 1 is an antenna, 2 is a receiver, 3 is an A/D converter, 4 is a radar signal processing device, 5a and 5b are 6-bit A/D converters, 6 is a switch, 7 is a D/A converter, and 8 is a 9 is an error detection circuit, and 10 is a register. In the drawings, the same or corresponding parts are denoted by the same reference numerals.
Claims (1)
換器を組合せて構成される直並列型アナログ・デ
イジタル変換器と、上記直並列型アナログ・デイ
ジタル変換器の出力段と上記直並列型アナログ・
デイジタル変換器を構成する上位並列型アナログ
・デイジタル変換器の出力段とを切換選択し、上
記上位並列型アナログ・デイジタル変換器を低分
解能高速Ａ／Ｄコンバータとして用いるためのス
イツチとを設けたことを特徴とするアナログ・デ
イジタル変換装置。 A series/parallel analog/digital converter configured by combining two low-resolution parallel analog/digital converters, an output stage of the series/parallel analog/digital converter, and the series/parallel analog/digital converter.
A switch is provided for selecting the output stage of the upper parallel type analog-to-digital converter constituting the digital converter and using the upper parallel type analog-to-digital converter as a low-resolution high-speed A/D converter. An analog-to-digital converter featuring:
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP15504786U JPS6361828U (en) | 1986-10-09 | 1986-10-09 |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP15504786U JPS6361828U (en) | 1986-10-09 | 1986-10-09 |
Publications (1)
| Publication Number | Publication Date |
|---|---|
| JPS6361828U true JPS6361828U (en) | 1988-04-23 |
Family
ID=31075395
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP15504786U Pending JPS6361828U (en) | 1986-10-09 | 1986-10-09 |
Country Status (1)
| Country | Link |
|---|---|
| JP (1) | JPS6361828U (en) |
-
1986
- 1986-10-09 JP JP15504786U patent/JPS6361828U/ja active Pending