JPS6347396B2 - - Google Patents

Info

Publication number
JPS6347396B2
JPS6347396B2 JP22139182A JP22139182A JPS6347396B2 JP S6347396 B2 JPS6347396 B2 JP S6347396B2 JP 22139182 A JP22139182 A JP 22139182A JP 22139182 A JP22139182 A JP 22139182A JP S6347396 B2 JPS6347396 B2 JP S6347396B2
Authority
JP
Japan
Prior art keywords
demultiplexer
data
output
latch
input
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Expired
Application number
JP22139182A
Other languages
English (en)
Japanese (ja)
Other versions
JPS59111499A (ja
Inventor
Tadanobu Nikaido
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Nippon Telegraph and Telephone Corp
Original Assignee
Nippon Telegraph and Telephone Corp
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Nippon Telegraph and Telephone Corp filed Critical Nippon Telegraph and Telephone Corp
Priority to JP22139182A priority Critical patent/JPS59111499A/ja
Publication of JPS59111499A publication Critical patent/JPS59111499A/ja
Publication of JPS6347396B2 publication Critical patent/JPS6347396B2/ja
Granted legal-status Critical Current

Links

Classifications

    • H—ELECTRICITY
    • H04—ELECTRIC COMMUNICATION TECHNIQUE
    • H04Q—SELECTING
    • H04Q11/00—Selecting arrangements for multiplex systems
    • H04Q11/04—Selecting arrangements for multiplex systems for time-division multiplexing

Landscapes

  • Engineering & Computer Science (AREA)
  • Computer Networks & Wireless Communication (AREA)
  • Use Of Switch Circuits For Exchanges And Methods Of Control Of Multiplex Exchanges (AREA)
JP22139182A 1982-12-17 1982-12-17 時間スイツチ回路 Granted JPS59111499A (ja)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP22139182A JPS59111499A (ja) 1982-12-17 1982-12-17 時間スイツチ回路

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP22139182A JPS59111499A (ja) 1982-12-17 1982-12-17 時間スイツチ回路

Publications (2)

Publication Number Publication Date
JPS59111499A JPS59111499A (ja) 1984-06-27
JPS6347396B2 true JPS6347396B2 (zh) 1988-09-21

Family

ID=16766032

Family Applications (1)

Application Number Title Priority Date Filing Date
JP22139182A Granted JPS59111499A (ja) 1982-12-17 1982-12-17 時間スイツチ回路

Country Status (1)

Country Link
JP (1) JPS59111499A (zh)

Families Citing this family (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPH0779515B2 (ja) * 1987-02-04 1995-08-23 日本電信電話株式会社 時分割交換スイツチ
JPS6478095A (en) * 1987-09-18 1989-03-23 Nippon Telegraph & Telephone Time switch

Also Published As

Publication number Publication date
JPS59111499A (ja) 1984-06-27

Similar Documents

Publication Publication Date Title
JP2500740B2 (ja) デュアルポ―トメモリ
KR100945968B1 (ko) 반도체기억장치
KR100206063B1 (ko) 동기 낸드 디램 구조
US4825411A (en) Dual-port memory with asynchronous control of serial data memory transfer
JP3386705B2 (ja) 半導体記憶装置およびそのバーストアドレスカウンタ
US7263023B2 (en) Semiconductor memory device having memory architecture supporting hyper-threading operation in host system
JPH01310433A (ja) 倍密度走査用ラインメモリ
US5748635A (en) Multiport datapath system
EP0520425B1 (en) Semiconductor memory device
US5787273A (en) Multiple parallel identical finite state machines which share combinatorial logic
JPH0391188A (ja) Ｆｉｆｏメモリ
JP3748648B2 (ja) バーストカウンター回路
JPS6347396B2 (zh)
EP1638108A1 (en) Multi-port memory
JPH0129352B2 (zh)
JP3057728B2 (ja) 半導体記憶装置
JP3090104B2 (ja) 半導体メモリ装置
CA1191211A (en) Electronic time switch
JPH0328879B2 (zh)
JP2728395B2 (ja) 半導体記憶装置
JP2963953B2 (ja) 半導体集積回路
CN116486856A (zh) 一种数据读写电路
JPH06290584A (ja) 半導体記憶装置
JPH073745B2 (ja) 直列ｆｉｆｏメモリ
JP3154507B2 (ja) 半導体記憶装置