JPS6345857A - Semiconductor device - Google Patents
Semiconductor deviceInfo
- Publication number
- JPS6345857A JPS6345857A JP19080286A JP19080286A JPS6345857A JP S6345857 A JPS6345857 A JP S6345857A JP 19080286 A JP19080286 A JP 19080286A JP 19080286 A JP19080286 A JP 19080286A JP S6345857 A JPS6345857 A JP S6345857A
- Authority
- JP
- Japan
- Prior art keywords
- metal
- contact
- semiconductor
- wiring
- diffusion region
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Pending
Links
- 239000004065 semiconductor Substances 0.000 title claims abstract description 25
- 229910052751 metal Inorganic materials 0.000 claims abstract description 34
- 239000002184 metal Substances 0.000 claims abstract description 34
- 238000009792 diffusion process Methods 0.000 claims abstract description 30
- 239000012535 impurity Substances 0.000 claims abstract description 11
- 239000000758 substrate Substances 0.000 abstract description 10
- PCHJSUWPFVWCPO-UHFFFAOYSA-N gold Chemical compound [Au] PCHJSUWPFVWCPO-UHFFFAOYSA-N 0.000 abstract description 4
- 239000010931 gold Substances 0.000 abstract description 4
- 229910052737 gold Inorganic materials 0.000 abstract description 4
- NRTOMJZYCJJWKI-UHFFFAOYSA-N Titanium nitride Chemical compound [Ti]#N NRTOMJZYCJJWKI-UHFFFAOYSA-N 0.000 abstract description 3
- 230000010354 integration Effects 0.000 abstract description 2
- 230000006378 damage Effects 0.000 abstract 1
- 238000000034 method Methods 0.000 abstract 1
- 239000010410 layer Substances 0.000 description 9
- 238000010586 diagram Methods 0.000 description 3
- 230000015556 catabolic process Effects 0.000 description 2
- 229910021420 polycrystalline silicon Inorganic materials 0.000 description 2
- 229920005591 polysilicon Polymers 0.000 description 2
- 210000004709 eyebrow Anatomy 0.000 description 1
- 238000010438 heat treatment Methods 0.000 description 1
- 238000009413 insulation Methods 0.000 description 1
- 239000011229 interlayer Substances 0.000 description 1
- 238000004519 manufacturing process Methods 0.000 description 1
- 239000012528 membrane Substances 0.000 description 1
Classifications
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/0001—Technical content checked by a classifier
- H01L2924/0002—Not covered by any one of groups H01L24/00, H01L24/00 and H01L2224/00
Landscapes
- Internal Circuitry In Semiconductor Integrated Circuit Devices (AREA)
- Electrodes Of Semiconductors (AREA)
Abstract
Description
【発明の詳細な説明】
〔産業上の利用分野〕
本発明は半導体装置に関し、特に不純物拡散領域と金属
配線とを接続する半導体装置の配線構造に関する。DETAILED DESCRIPTION OF THE INVENTION [Field of Industrial Application] The present invention relates to a semiconductor device, and particularly to a wiring structure of a semiconductor device that connects an impurity diffusion region and a metal wiring.
従来の半導体集積装置における配線構造は、半導体基板
に能動領域を形成し、半導体全面を被う絶縁膜の必要個
所にピアホールを設け、−ｍ的には、ポリシリコンの薄
い層を介したアルミニューム等による電極配線を有した
構造を成している。The wiring structure in conventional semiconductor integrated devices is such that an active region is formed on a semiconductor substrate, and peer holes are provided at necessary locations in an insulating film that covers the entire surface of the semiconductor. It has a structure with electrode wiring according to etc.
従来のＣＭＯＳインバータの構造の一例として、第２図
に回路図、第３図（ａ）、（ｂ）に平面図とそのｎ−ｎ
”断面図を示している。図中、１はゲー１〜．２’ 、
３’はドレイン、ソース側のアレミニラム（金属）配線
、５は絶縁層、６はロコス酸化膜、７はトレイン、８は
ソース、９はＮ−ウェル、１０はＰ型基板、１１はポリ
シリコン層、１２はコンタクトウェル拡散層を示す。As an example of the structure of a conventional CMOS inverter, Fig. 2 is a circuit diagram, and Figs. 3 (a) and (b) are plan views and their n-n diagrams.
``A cross-sectional view is shown. In the figure, 1 is a gage 1~.2',
3' is drain, source side areminium (metal) wiring, 5 is insulating layer, 6 is LOCOS oxide film, 7 is train, 8 is source, 9 is N-well, 10 is P type substrate, 11 is polysilicon layer , 12 indicate contact well diffusion layers.
一般に、ＭＯＳＦＥＴに於いては、基板電圧効果がある
ため、基板電位を一定の値（電源電位が、又は接地電位
）に保つ必要があるが、従来の配線構造では、ウェル９
及び基板（サブストレート）１０への接続を取るための
拡散領域をＭＯ３ＦＥＴのソース領域７、ドレイン領域
８以外に必要とするので、高集積化を阻む原因となって
いた。Generally, in MOSFETs, it is necessary to maintain the substrate potential at a constant value (power supply potential or ground potential) due to the substrate voltage effect, but in the conventional wiring structure, the well 9
In addition, a diffusion region for connection to the substrate 10 is required in areas other than the source region 7 and drain region 8 of the MO3FET, which hinders high integration.
本発明の目的は、このような問題点を解決し、高集積化
を可能とした半導体装置を提供することにある。An object of the present invention is to solve these problems and provide a semiconductor device that can be highly integrated.
本発明の構成は、半導体に対する拡散係数の大きい第１
の金属からなる金属配線を有する半導体装置に於いて、
少くとも前記半導体の不純物拡散領域と前記金属配線と
の接触部に、前記半導体に対する拡散係数の小さい第２
の金属を選択的に介在させ、前記第２の金属を介在させ
ない個所は前記第１の金属配線が直接に前記不純物拡散
領域に接続されるようにしたことを特徴とする。The structure of the present invention has a first structure with a large diffusion coefficient for semiconductors.
In a semiconductor device having metal wiring made of metal,
At least in the contact area between the impurity diffusion region of the semiconductor and the metal wiring, a second layer having a small diffusion coefficient with respect to the semiconductor is provided.
The first metal wiring is selectively interposed therebetween, and the first metal wiring is directly connected to the impurity diffusion region at a portion where the second metal is not interposed.
次に本発明について図面を参照して説明する。 Next, the present invention will be explained with reference to the drawings.
第１図（ａ）、（ｂ）は本発明の一実施例を示す平面図
およびそのＩ−Ｉ’部分の断面図であり、第２図のＣＭ
ＯＳインバータの回路を示してイル。図中、１はＭｏＳ
のゲート、２，３は半導体に対する拡散係数の大きい金
属、例えは金からなる配線、４は半導体に対する拡散係
数の小さい金属、例えは窒化チタンからなる金属マスク
、５は眉間絶縁膜、６はロコス酸化膜、７はソース（Ｐ
”）、８はドレイン（Ｐ”）である。FIGS. 1(a) and 1(b) are a plan view showing an embodiment of the present invention and a sectional view taken along line II' of the same;
This figure shows the circuit of the OS inverter. In the figure, 1 is MoS
gate, 2 and 3 are wirings made of a metal with a large diffusion coefficient for semiconductors, such as gold, 4 is a metal mask made of a metal with a small diffusion coefficient for semiconductors, such as titanium nitride, 5 is an insulating film between the eyebrows, and 6 is a locos. oxide film, 7 is the source (P
”), 8 is the drain (P”).
ソース７に於けるコンタクトには、金が直接に不純物拡
散層に接触し、ある温度で、ソースのジャンクション深
さより決まる一定時間熱処理することにより、図に示す
様に、部分的なジャンクション破壊２０がなされ、電源
■ＤＤとウェル（ｗｅｌｌ）９及びソース７との接続が
、１個のコンタクトにより形成される。一方、ドレイン
８側は、窒化チタン（４）により、金の熱拡散が防止さ
れるため、ジャンクションの破壊は起らない。本実施例
は、ウェルコンタクト、サブストレートコンタクト専用
の拡散領域を必要としないことは明らかであり、また必
要な接続点も減少している。In the contact in the source 7, the gold is in direct contact with the impurity diffusion layer, and by heat treatment at a certain temperature for a certain period of time determined by the junction depth of the source, a partial junction breakdown 20 is caused as shown in the figure. The connection between the power supply DD and the well 9 and source 7 is formed by one contact. On the other hand, on the drain 8 side, thermal diffusion of gold is prevented by titanium nitride (4), so no junction breakdown occurs. It is clear that this embodiment does not require dedicated diffusion regions for well contacts and substrate contacts, and also reduces the number of required connection points.
以上説明したように、本発明は半導体に対して拡散係数
の大きい金属で配線を形成し、任意の不純物拡散層との
接続点を半導体に対して拡散係数の小さい金属で選択的
にマスクし、マスクされていない接続点に於けるＰ−Ｎ
接合を配線金属の拡散によって破壊することにより、Ｍ
ＯＳＦＥＴのソース部と、サブストレートコンタクト又
はウェルコンタクトとを１つの接点として形成でき、サ
ブストレートコンタクト又はウェルコンタクトを形成す
る専用の不純物拡散層が不要となるので、集積回路のよ
り高集積化ができ、かつ能動的接点の減少により、製遺
歩留りも向上するという効果がある。As explained above, the present invention forms wiring with a metal having a large diffusion coefficient relative to the semiconductor, selectively masks connection points with arbitrary impurity diffusion layers with a metal having a small diffusion coefficient relative to the semiconductor, P-N at unmasked connection points
By destroying the junction by diffusion of wiring metal, M
The source part of the OSFET and the substrate contact or well contact can be formed as one contact, and a dedicated impurity diffusion layer for forming the substrate contact or well contact is not required, so that the integrated circuit can be highly integrated. , and the reduction in active contact points has the effect of improving manufacturing yield.
第１図（ａ＞、（ｂ）は本発明の一実施例のＣＭＯＳイ
ンバータの平面図およびそのＩ−１’に於ける断面図、
第２図は従来のＣＭＯＳインバータの一例の回路図、第
３図（ａ）、（ｂ）は従来のＣＭＯＳインバータの一例
の平面図およびそのｎ−ｍ’断面図である。
１・・・ゲート、２，２′・・・ドレイン側の金属配線
、３．３′・・・ソース側の金属配線、４・・・低拡散
係数を有する金属マスク、５・・・層間絶縁膜、６・・
・ロコス酸化膜、７・・・ソース、８・・・ドレイン、
９・・・Ｎ型ウェル、１０・・・Ｐ型基板、１１・・・
ポリシリコン層、１２・・・コンタク１−ウェル用拡散
層。
＼、−−ｔFIG. 1 (a>, (b) is a plan view of a CMOS inverter according to an embodiment of the present invention and a cross-sectional view at I-1' thereof,
FIG. 2 is a circuit diagram of an example of a conventional CMOS inverter, and FIGS. 3(a) and 3(b) are a plan view and an nm' sectional view of an example of a conventional CMOS inverter. 1... Gate, 2, 2'... Metal wiring on the drain side, 3.3'... Metal wiring on the source side, 4... Metal mask with a low diffusion coefficient, 5... Interlayer insulation Membrane, 6...
・Locos oxide film, 7...source, 8...drain,
9...N type well, 10...P type substrate, 11...
Polysilicon layer, 12... contact 1-well diffusion layer. \,--t
Claims (1)
金属配線を有する半導体装置に於いて、少くとも前記半
導体の不純物拡散領域と前記金属配線との接触部に、前
記半導体に対する拡散係数の小さい第２の金属を選択的
に介在させ、前記第２の金属を介在させない個所は前記
第１の金属配線が直接に前記不純物拡散領域に接続され
るようにしたことを特徴とする半導体装置。In a semiconductor device having a metal wiring made of a first metal having a large diffusion coefficient with respect to the semiconductor, a second metal having a small diffusion coefficient with respect to the semiconductor is provided at least at a contact portion between an impurity diffusion region of the semiconductor and the metal wiring. 1. A semiconductor device, wherein a metal is selectively interposed and the first metal wiring is directly connected to the impurity diffusion region at a portion where the second metal is not interposed.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP19080286A JPS6345857A (en) | 1986-08-13 | 1986-08-13 | Semiconductor device |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP19080286A JPS6345857A (en) | 1986-08-13 | 1986-08-13 | Semiconductor device |
Publications (1)
| Publication Number | Publication Date |
|---|---|
| JPS6345857A true JPS6345857A (en) | 1988-02-26 |
Family
ID=16263986
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP19080286A Pending JPS6345857A (en) | 1986-08-13 | 1986-08-13 | Semiconductor device |
Country Status (1)
| Country | Link |
|---|---|
| JP (1) | JPS6345857A (en) |
Citations (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPS5856977A (en) * | 1981-09-30 | 1983-04-04 | ヤマハ発動機株式会社 | Cowling structure of head lamp of motorcycle |
| JPS5877257A (en) * | 1981-11-04 | 1983-05-10 | Hitachi Ltd | Superiorly high reliable electrode |
-
1986
- 1986-08-13 JP JP19080286A patent/JPS6345857A/en active Pending
Patent Citations (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPS5856977A (en) * | 1981-09-30 | 1983-04-04 | ヤマハ発動機株式会社 | Cowling structure of head lamp of motorcycle |
| JPS5877257A (en) * | 1981-11-04 | 1983-05-10 | Hitachi Ltd | Superiorly high reliable electrode |
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