JPH08316421A - Semiconductor integrated circuit device - Google Patents

Abstract

PURPOSE: To form a protective element whose withstand voltage is lower than that of an inner circuit element by using a diode wherein reach-through withstand voltage is used. CONSTITUTION: A double diffusion layer structure constituted of an N<-> type diffusion layer 5 and an N<-> type diffusion layer 6 is formed in a first element forming region wherein element isolation is performed with a field oxide film 2, and a P<+> type diffusion layer 7 is formed on a second element forming region. A P-type guard ring layer 3 arranged under the field oxide film 2 and the N<+> type diffusion layer 6 as a cathode are made adjacent to each other. Thereby reach-through withstand voltage can be made lower than the withstand voltage of an inner transistor.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a semiconductor integrated circuit device, and more particularly to a protection circuit element.

[0002]

2. Description of the Related Art FIG. 2 is a sectional view of a semiconductor chip showing an example of a conventional protection off-buffer element.

In a high voltage system (power supply voltage 10 V to 10 V), as shown in FIG. 2, a field oxide film 2 provided on the surface of a p-type silicon substrate 1 for partitioning an element formation region and a p provided below the field oxide film 2. Type guard ring layer 3, a gate oxide film 4 formed on the surface of the element formation region, a gate electrode 11 selectively formed on the gate oxide film 4, and a mask of the gate electrode 11 and the field oxide film 2. As a deep n ⁻ formed by ion-implanting impurities into the element formation region as
The type diffusion layer 6 and the shallow n provided in the n ⁻ type diffusion layer 6
^A source / drain region having a double diffusion layer structure with the ⁺ type diffusion layer 7, an interlayer insulating film 8 provided on the surface including the gate electrode 11, and n of a contact hole provided in the interlayer insulating film 8.
^It has a drain electrode 12 and a source electrode 13 which are formed so as to be connected to the ⁺ type diffusion layer 6.

This structure has a high voltage system MO for logic circuits.
It is the same as the S-transistor, and is used as an off-buffer by setting the gate electrode to the same potential as the substrate potential as shown in the equivalent circuit of FIG.

When this off-buffer is used as a protection element, its operation will be described in order as follows.

(1) A high voltage pulse is applied to the drain electrode.

(2) The junction diode D in the drain diffusion layer causes a breakdown.

(3) The generated hole of the electron-hole pair raises the potential under the gate electrode.

(4) Since the parasitic npn type bipolar transistor B is turned on, the on resistance after the breakdown can be reduced.

[0010] In this case, the current to flow through the drain resistor R _D, the source resistance R _S, a phenomenon in which the drain resistor R _D, the source resistance R _S generates heat occurs.

[0011]

In this conventional semiconductor integrated circuit device, since the structure of the protection circuit element is the same as that of the internal logic circuit, its breakdown voltage is also the same. Also,
When the concentration of the n ⁻ -type diffusion layer in the source / drain region is low and the drain resistance and the source are high, the parasitic npn-type bipolar transistor is turned on, so that an overcurrent flows,
There is a problem that junction destruction is caused due to heat generation in the drain region and the source region.

For these reasons, when the off-buffer is used as a protection element, it is necessary to increase its occupied area to disperse the current.

An object of the present invention is to provide a semiconductor integrated circuit having a protection element having a lower breakdown voltage than an internal circuit element.

[0014]

A semiconductor integrated circuit device according to the present invention is a field insulating device which is formed on one main surface of a semiconductor substrate of one conductivity type and isolates adjacent first and second device forming regions from each other. Film, a guard ring layer of one conductivity type provided under the field insulating film, a deep low impurity concentration diffusion layer of the opposite conductivity type formed on the surface of the semiconductor substrate in the first element formation region, and the low diffusion layer. A double diffusion layer structure formed on the impurity concentration diffusion layer and including a shallow high impurity concentration diffusion layer adjacent to the guard ring layer, and one conductivity formed on the surface of the semiconductor substrate in the second element formation region. Type high impurity concentration diffusion layer.

[0015]

Next, the present invention will be described with reference to the drawings.

FIG. 1 is a sectional view of a semiconductor chip showing an embodiment of the present invention.

As shown in FIG. 1, first, the impurity concentration is 1
Under the field oxide film 2 formed by locally oxidizing the surface of the p-type silicon substrate 1 of × 10 ¹⁴ to 1 × 10 ¹⁶ cm ⁻³ , the impurity concentration is 1 × 10 ¹⁶ to 1 × 10 ¹⁹ cm ⁻³ . A p-type guard ring layer 3 having a depth of 0.2 to 1 μm is formed, and a gate oxide film 4 having a film thickness of 40 to 100 nm is formed on the surfaces of the first and second element formation regions which are partitioned by the field oxide film 2 and are adjacent to each other. To form. The impurity concentration in the first element formation region is 1 × 10 ¹⁶ to 1 × 10 ¹⁹ cm ⁻³ and the depth is 0.3 to 2
An n ⁻ -type diffusion layer 5 having a thickness of 0.1 μm is formed on the n ⁻ -type diffusion layer 5 with an impurity concentration of 1 × 10 ¹⁹ to 1 × 10 ²² cm ⁻³ and a depth of 0.1 to 0.5 μm. ^A double diffusion layer formed with the ⁺ type diffusion layer 6 is formed.

Next, a p ⁺ type diffusion layer 7 having an impurity concentration of 1 × 10 ¹⁹ to 1 × 10 ²² cm ^-3 and a depth of 0.2 to 1 μm is formed in the second element formation region. Next, the interlayer insulating film 8 is formed on the entire surface.
Is deposited and selectively etched to form a contact hole on the n ⁺ type diffusion layer 6 and the p ⁺ type diffusion layer 7, and a metal film is deposited and patterned on the surface including the contact hole to form a contact hole. A cathode electrode 9 connected to the n ⁺ type diffusion layer 6 and an anode electrode 10 connected to the p ⁺ type diffusion layer 7 are formed.

Although not shown, the cathode electrode 9 is connected to an external terminal and is also protected by the gate electrode of the transistor to be protected (when the protection element is used for input circuit protection) or protection. Drain of the power transistor (when the protection element is used for output circuit protection) or the like.

In the semiconductor integrated circuit device having such a structure, since the n ⁺ type diffusion layer 6 is adjacent to the p type guard ring layer 3, the extension of the depletion layer is limited and the reach through breakdown voltage is higher than that of the internal transistor. Low. Therefore, it is possible to form a protection diode whose breakdown voltage is lower than that of the internal transistor without adding a special process. Further, since the current flows without passing through the n ⁻ type diffusion layer 5, heat generation is suppressed and junction breakdown is prevented.

[0021]

As described above, according to the present invention, the first conductive type semiconductor substrate is divided into the first oxide film on the surface thereof by the field oxide film.
Of the low-concentration reverse-conductivity type diffusion layer formed in the element formation region and the high-concentration reverse-conductivity type diffusion layer adjacent to the one-conductivity type guard ring layer provided above the field oxide film and below the field oxide film. The extent of the depletion layer when a voltage pulse is applied to the cathode electrode is made smaller than that in the case where the high-concentration reverse conductivity type diffusion layer of the internal transistor and the one conductivity type guard ring layer are separated, and the reach-through breakdown voltage is reduced. It is possible to realize a protection element that is lower than the internal transistor. Actually, the impurity concentration of the n ⁻ type diffusion layer is 1 × 10 ¹⁶ to 1 × 10 ¹⁹ c.
m ⁻³ , depth 0.3 to 2 μm, impurity concentration of p-type guard ring 1 × 10 ¹⁶ to 1 × 10 ¹⁹ cm ⁻³ , depth 0.2 to
In case of 1 μm, the breakdown voltage of the internal transistor is 20-80V
On the other hand, the withstand voltage of the protection diode of the present invention is 2 to
It becomes 30V.

Further, since all of these diffusion layers can be formed by self-alignment, there is an advantage that they can be formed in the same step as the internal transistor without adding a special step.

Further, the gate electrode required in the conventional MOS type protection element can be omitted, and the protection element can be formed with a smaller occupied area. Moreover, since the breakdown voltage is lower than that of the internal transistor, an overcurrent does not flow to the internal transistor. Therefore, unlike the conventional example, it is not necessary to disperse an excessive current in a large area, and the protection element can be formed with a smaller occupied area.

Further, since an excessive current flows from the high concentration n type diffusion layer to the p type guard ring layer, it does not pass through the low concentration n type diffusion layer. Therefore, the generation of heat is also suppressed, and junction destruction is prevented.

[Brief description of drawings]

FIG. 1 is a sectional view of a semiconductor chip showing an embodiment of the present invention.

FIG. 2 is a sectional view of a semiconductor chip showing an example of a conventional semiconductor integrated circuit device.

FIG. 3 is a diagram showing an equivalent circuit of FIG.

[Explanation of symbols]

1 p-type silicon substrate 1 2 field oxide film 3 guard ring layer 4 gate oxide film 5 n ^- type diffusion layer 6 n ⁺ type diffusion layer 7 p ⁺ type diffusion layer 8 interlayer insulating film 9 cathode electrode 10 anode electrode 11 gate electrode 12 Drain electrode 13 Source electrode

Claims (1)

[Claims] 1. A field insulating film formed on one main surface of a one-conductivity-type semiconductor substrate to isolate adjacent first and second element forming regions from each other, and a field insulating film provided below the field insulating film. A conductive guard ring layer, and the first
From the deep low impurity concentration diffusion layer of the opposite conductivity type formed on the surface of the semiconductor substrate in the element formation region and the shallow high impurity concentration diffusion layer formed above the low impurity concentration diffusion layer and adjacent to the guard ring layer. And a double diffusion layer structure
A semiconductor integrated circuit device, comprising: one conductivity type high impurity concentration diffusion layer formed on the surface of the semiconductor substrate in the second element formation region.