JPH0677490A - Vertical field-effect transistor - Google Patents
Vertical field-effect transistorInfo
- Publication number
- JPH0677490A JPH0677490A JP4226806A JP22680692A JPH0677490A JP H0677490 A JPH0677490 A JP H0677490A JP 4226806 A JP4226806 A JP 4226806A JP 22680692 A JP22680692 A JP 22680692A JP H0677490 A JPH0677490 A JP H0677490A
- Authority
- JP
- Japan
- Prior art keywords
- source
- source region
- parasitic
- contact
- semiconductor substrate
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Pending
Links
- 230000005669 field effect Effects 0.000 title claims description 5
- 239000004065 semiconductor Substances 0.000 claims abstract description 14
- 239000000758 substrate Substances 0.000 claims abstract description 14
- 230000000694 effects Effects 0.000 claims description 2
- 230000003071 parasitic effect Effects 0.000 abstract description 11
- XAGFODPZIPBFFR-UHFFFAOYSA-N aluminium Chemical compound [Al] XAGFODPZIPBFFR-UHFFFAOYSA-N 0.000 abstract description 8
- 229910052782 aluminium Inorganic materials 0.000 abstract description 8
- 239000011229 interlayer Substances 0.000 abstract description 7
- 239000010410 layer Substances 0.000 description 22
- 238000009792 diffusion process Methods 0.000 description 13
- 229910021420 polycrystalline silicon Inorganic materials 0.000 description 8
- 229920005591 polysilicon Polymers 0.000 description 8
- 238000004519 manufacturing process Methods 0.000 description 5
- 238000000059 patterning Methods 0.000 description 4
- 239000012535 impurity Substances 0.000 description 3
- 230000015556 catabolic process Effects 0.000 description 2
- 238000010438 heat treatment Methods 0.000 description 2
- 229920002120 photoresistant polymer Polymers 0.000 description 2
- 230000005856 abnormality Effects 0.000 description 1
- 230000015572 biosynthetic process Effects 0.000 description 1
- 238000005530 etching Methods 0.000 description 1
- 238000000034 method Methods 0.000 description 1
- 229910052710 silicon Inorganic materials 0.000 description 1
- 239000010703 silicon Substances 0.000 description 1
Classifications
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
- H01L29/68—Types of semiconductor device ; Multistep manufacturing processes therefor controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched
- H01L29/76—Unipolar devices, e.g. field effect transistors
- H01L29/772—Field effect transistors
- H01L29/78—Field effect transistors with field effect produced by an insulated gate
- H01L29/7801—DMOS transistors, i.e. MISFETs with a channel accommodating body or base region adjoining a drain drift region
- H01L29/7802—Vertical DMOS transistors, i.e. VDMOS transistors
-
- C—CHEMISTRY; METALLURGY
- C04—CEMENTS; CONCRETE; ARTIFICIAL STONE; CERAMICS; REFRACTORIES
- C04B—LIME, MAGNESIA; SLAG; CEMENTS; COMPOSITIONS THEREOF, e.g. MORTARS, CONCRETE OR LIKE BUILDING MATERIALS; ARTIFICIAL STONE; CERAMICS; REFRACTORIES; TREATMENT OF NATURAL STONE
- C04B41/00—After-treatment of mortars, concrete, artificial stone or ceramics; Treatment of natural stone
- C04B41/45—Coating or impregnating, e.g. injection in masonry, partial coating of green or fired ceramics, organic coating compositions for adhering together two concrete elements
- C04B41/52—Multiple coating or impregnating multiple coating or impregnating with the same composition or with compositions only differing in the concentration of the constituents, is classified as single coating or impregnation
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/40—Electrodes ; Multistep manufacturing processes therefor
- H01L29/41—Electrodes ; Multistep manufacturing processes therefor characterised by their shape, relative sizes or dispositions
- H01L29/417—Electrodes ; Multistep manufacturing processes therefor characterised by their shape, relative sizes or dispositions carrying the current to be rectified, amplified or switched
- H01L29/41725—Source or drain electrodes for field effect devices
- H01L29/41766—Source or drain electrodes for field effect devices with at least part of the source or drain electrode having contact below the semiconductor surface, e.g. the source or drain electrode formed at least partially in a groove or with inclusions of conductor inside the semiconductor
Landscapes
- Engineering & Computer Science (AREA)
- Ceramic Engineering (AREA)
- Chemical & Material Sciences (AREA)
- Microelectronics & Electronic Packaging (AREA)
- Power Engineering (AREA)
- Condensed Matter Physics & Semiconductors (AREA)
- General Physics & Mathematics (AREA)
- Computer Hardware Design (AREA)
- Physics & Mathematics (AREA)
- Materials Engineering (AREA)
- Structural Engineering (AREA)
- Organic Chemistry (AREA)
- Insulated Gate Type Field-Effect Transistor (AREA)
- Electrodes Of Semiconductors (AREA)
Abstract
Description
【０００１】[0001]
【産業上の利用分野】この発明は縦型電界効果トランジ
スタ（以下縦型ＭＯＳＦＥＴという）の構造に関し、特
に２重拡散構造を有する縦型ＭＯＳＦＥＴの構造に関す
る。BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to the structure of a vertical field effect transistor (hereinafter referred to as vertical MOSFET), and more particularly to the structure of a vertical MOSFET having a double diffusion structure.
【０００２】[0002]
【従来の技術】従来、この種の縦型ＭＯＳＦＥＴの構造
はＮチャンネルを例にとると、図３に示すように、ドレ
インとしてえ作用するＮ- 型半導体基板７の表面にベー
スとなるＰ型拡散層６とその内部にソースと等なるＮ+
型拡散層５とをゲートポリシリコン３をマスクに２重拡
散構造により形成し、ソースアルミ電極１とソース領域
Ｎ+ 型拡散層５とのコンタクトはＮ- 型半導体基板７の
表面でとる構造なっていた。Conventionally, taking the structure N-channel of this type of vertical MOSFET as an example, as shown in FIG. 3, it acts example as a drain N - P-type as a base on the surface of the type semiconductor substrate 7 Diffusion layer 6 and N + inside the diffusion layer 6 to serve as a source
The type diffusion layer 5 is formed by a double diffusion structure using the gate polysilicon 3 as a mask, and the source aluminum electrode 1 and the source region N + type diffusion layer 5 are in contact with each other on the surface of the N − type semiconductor substrate 7. Was there.
【０００３】図４に示す断面図を用いて、製法について
説明する。The manufacturing method will be described with reference to the sectional view shown in FIG.
【０００４】一導電型（例えばＮ- 型）半導体基板７に
ゲート酸化膜４、その上に例えばポリシリコン膜を形成
し、それをパターンニングして、ポリシリコンでなるゲ
ート３を形成する。ゲートポリシリコン３をマスクに他
導型（この場合Ｐ型）の不純物を注入し、熱拡散を適用
してベース層６を形成する（図４−Ａ参照）。A gate oxide film 4 is formed on a semiconductor substrate 7 of one conductivity type (for example, N − type), a polysilicon film is formed on the gate oxide film 4, and the gate oxide film 4 is patterned to form a gate 3 made of polysilicon. Using the gate polysilicon 3 as a mask, another conductivity type (P type in this case) impurities are implanted, and thermal diffusion is applied to form the base layer 6 (see FIG. 4-A).
【０００５】次にベース層６の表面の一部に例えばホト
レジスト等によりマスク２１を形成し、ゲートポリシリ
コン３とマスク２１とをマスクに一導電型（この場合Ｎ
型）の不純物を注入し、熱処理を行ってソース層５を形
成する（図４−Ｂ参照）。次に表面に酸化膜よりなる層
間膜２を形成し、ホトレジストによるマスク（図示せ
ず）を利用してコンタクトホールを形成する（図４−Ｃ
参照）。Next, a mask 21 is formed on a part of the surface of the base layer 6 with, for example, a photoresist, and the gate polysilicon 3 and the mask 21 are used as masks to form one conductivity type (N in this case).
(Type) impurities are implanted and heat treatment is performed to form the source layer 5 (see FIG. 4-B). Next, an interlayer film 2 made of an oxide film is formed on the surface, and contact holes are formed using a mask (not shown) made of photoresist (FIG. 4-C).
reference).
【０００６】その後、アルミによりソース電極１を形成
して、図３に示す縦型ＭＯＳＦＥＴが完成する。After that, the source electrode 1 is formed of aluminum to complete the vertical MOSFET shown in FIG.
【０００７】[0007]
【発明が解決しようとする課題】ところで、上記の従来
の縦型ＭＯＳＦＥＴは、ソースアルミ電極とソース領域
Ｎ+ 型各散層とのコンタクトをＮ- 型半導体基板表面で
とる構造となっているので、縦型ＭＯＳＦＥＴに寄生す
るＮＰＮバイポーラトランジスタ１６のベース抵抗１７
を、低減することができないため異常時に微小の電流が
ベース抵抗１７に流れるとベース電位が上昇し、寄生Ｎ
ＰＮバイポーラトランジスタ１６がオンし、電流集中が
起き破壊に至るという欠点があった。By the way, the above-mentioned conventional vertical MOSFET has a structure in which the source aluminum electrode is in contact with each source region N + type diffusion layer on the surface of the N − type semiconductor substrate. , The base resistance 17 of the NPN bipolar transistor 16 parasitic on the vertical MOSFET
Since it cannot be reduced, if a minute current flows to the base resistor 17 at the time of abnormality, the base potential rises, and the parasitic N
There is a drawback that the PN bipolar transistor 16 is turned on, current concentration occurs and it is destroyed.
【０００８】[0008]
【課題を解決するための手段】この発明の縦型ＭＯＳＦ
ＥＴは、ドレインとして作用する半導体基板の表面にベ
ース領域とその内部にソース領域を形成したものにおい
て、半導体基板の表面をソース領域より深く選択的にエ
ッチングして、ソース領域の側面とコンタクトを取った
ソース電極を有することを特徴とする。A vertical MOSF of the present invention.
In ET, a base region and a source region are formed on the surface of a semiconductor substrate acting as a drain, and the surface of the semiconductor substrate is selectively etched deeper than the source region to make contact with the side surface of the source region. It is characterized by having a source electrode.
【０００９】[0009]
【作用】上記の構造によると、ベースとなる拡散層とソ
ース電極のコンタクトが大きくとれ、縦型ＭＯＳＦＥＴ
に寄生するＮＰＮバイポーラトランジスタのベース抵抗
を小さくすることができる。そのため微小の電流が流れ
ただけでは寄生ＮＰＮバイポーラトランジスタはオンせ
ず、破壊しない。According to the above structure, the contact between the diffusion layer serving as the base and the source electrode can be made large, and the vertical MOSFET
It is possible to reduce the base resistance of the NPN bipolar transistor parasitic on the. Therefore, the parasitic NPN bipolar transistor does not turn on and does not break even if a minute current flows.
【００１０】[0010]
【実施例】以下、この発明について図面を参照して説明
する。DESCRIPTION OF THE PREFERRED EMBODIMENTS The present invention will be described below with reference to the drawings.
【００１１】図１は、この発明の一実施例のＮチャンネ
ル縦型ＭＯＳＦＥＴの断面図である。FIG. 1 is a sectional view of an N-channel vertical MOSFET according to an embodiment of the present invention.
【００１２】図において７はＮ- 型半導体基板、６はＰ
型拡散層からなるベース領域、５はＮ+ 型拡散層でなる
ソース領域、４はゲート酸化膜、３はゲートポリシリコ
ン、２は層間膜、１はソースアルミ電極である。In the figure, 7 is an N -- type semiconductor substrate, and 6 is P.
A base region made of a type diffusion layer, 5 a source region made of an N + type diffusion layer, 4 a gate oxide film, 3 a gate polysilicon, 2 an interlayer film, 1 a source aluminum electrode.
【００１３】１のソースアルミ電極と５のソース領域と
のコンタクトは、２の層間膜を選択的にエッチングした
後、７の半導体基板を５のソース領域より深くエッチン
グして側面でコンタクトをとる構造とする。この実施例
によれば縦型ＭＯＳＦＥＴに寄生するＮＰＮバイポーラ
トランジスタのベース抵抗を小さくすることができ、微
小の電流が流れただけでは寄生ＮＰＮバイポーラトラン
ジスタはオンせず、電流集中による破壊は起こらない。The contact between the source aluminum electrode 1 and the source region 5 is such that the interlayer film 2 is selectively etched and then the semiconductor substrate 7 is etched deeper than the source region 5 to make contact on the side surface. And According to this embodiment, the base resistance of the NPN bipolar transistor parasitic on the vertical MOSFET can be reduced, and the parasitic NPN bipolar transistor does not turn on even if a minute current flows, and the breakdown due to current concentration does not occur.
【００１４】従来５のソース領域を形成する時行ってい
たマスク形成のパターンニングが不要となる。さらに、
これによりパターンの微細化が図れる素子構造となる。The patterning for mask formation, which has been conventionally performed when forming the source region 5, is not required. further,
As a result, the device structure has a finer pattern.
【００１５】図２を用い製法について説明する。The manufacturing method will be described with reference to FIG.
【００１６】従来例の製法と図４−Ａの工程までは同じ
である。ベース層６を形成後、同様にゲートポリシリコ
ン３をマスクにＮ型不純物を注入し、熱処理を行ってソ
ース層５を形成する。この場合従来の（図４−Ｂにおけ
る）マスク２１を必要としない（図２−Ａ参照）。The manufacturing method of the conventional example and the process of FIG. 4-A are the same. After forming the base layer 6, N-type impurities are similarly implanted using the gate polysilicon 3 as a mask and heat treatment is performed to form the source layer 5. In this case, the conventional mask 21 (in FIG. 4-B) is not required (see FIG. 2-A).
【００１７】次に従来例と同様（図４−Ｃと同様）層間
膜２を形成して、コンタクトホールを形成する（図２−
Ｂ参照）。Next, an interlayer film 2 is formed similarly to the conventional example (similar to FIG. 4-C) to form a contact hole (FIG. 2-
(See B).
【００１８】次に層間膜（又はそのパターンニングに用
いたマスク）をマスクに半導体（この場合シリコン）基
板をソース層５より若干深くエッチングする。Next, the semiconductor (silicon in this case) substrate is etched slightly deeper than the source layer 5 by using the interlayer film (or the mask used for its patterning) as a mask.
【００１９】なお、必要により、エッチングして表面を
現す部分のベース層にベース層と同型の高濃度層８を形
成することもできる。If necessary, a high-concentration layer 8 of the same type as the base layer can be formed on the base layer at the surface exposed by etching.
【００２０】高濃度層８はどの段階で形成してもよい。
高濃度層８の深さは例えばベース層６を越える深いもの
であってもよい（図示せず）。The high concentration layer 8 may be formed at any stage.
The depth of the high concentration layer 8 may be deeper than the base layer 6 (not shown).
【００２１】その後図１のようにソース電極をアルミに
より形成して本発明の縦型ＭＯＳＦＥＴとして完成す
る。After that, the source electrode is formed of aluminum as shown in FIG. 1 to complete the vertical MOSFET of the present invention.
【００２２】[0022]
【実施例２】第２の実施例として、だい１の実施例をＰ
チャンネルに応用することもできる（図示せず）。[Embodiment 2] As a second embodiment, P
It can also be applied to channels (not shown).
【００２３】[0023]
【発明の効果】以上説明したように、この発明はソース
電極とソース領域おのコンタクトをソース領域の側面で
とる構造にしたことにより、縦型ＭＯＳＦＥＴに寄生す
るバイポーラトランジスタのベース抵抗を小さくするこ
とができ、微小の電流が流れただけでは寄生バイポーラ
トランジスタはオンせず電流集中による破壊に至らな
い。また、リース電極とベース領域のコンタクトは、半
導体基板をソース領域より深くエッチングするのでソー
ス領域を形成する際のパターンニングが不要となる。さ
らにパターンニングが不要となるため素子構造の微細化
が図れるという効果がある。As described above, according to the present invention, the contact between the source electrode and the source region is formed on the side surface of the source region, thereby reducing the base resistance of the bipolar transistor parasitic on the vertical MOSFET. The parasitic bipolar transistor does not turn on and a breakdown due to current concentration does not occur even if a minute current flows. Further, since the contact between the lease electrode and the base region is etched deeper than the source region, the patterning when forming the source region is unnecessary. Furthermore, since patterning is unnecessary, there is an effect that the element structure can be miniaturized.
【図１】 この発明の縦型ＭＯＳＦＥＴの断面図であ
る。FIG. 1 is a sectional view of a vertical MOSFET of the present invention.
【図２】 その製法を説明する断面図である。FIG. 2 is a cross-sectional view explaining the manufacturing method.
【図３】 従来の縦型ＭＯＳＦＥＴの断面図である。FIG. 3 is a sectional view of a conventional vertical MOSFET.
【図４】 その製法を説明する断面図である。FIG. 4 is a cross-sectional view illustrating the manufacturing method.
１ ソースアルミ電極 ２ 層間膜 ３ ゲートポリシリコン ４ ゲート酸化膜 ５ Ｎ+ 型拡散層（ソース） ６ Ｐ型拡散層（ベース） ７ Ｎ- 型半導体基板1 Source Aluminum Electrode 2 Interlayer Film 3 Gate Polysilicon 4 Gate Oxide Film 5 N + Type Diffusion Layer (Source) 6 P Type Diffusion Layer (Base) 7 N − Type Semiconductor Substrate
Claims (2)
にベース領域と、その内部にソース領域とを形関した電
界効果トランジスタにおいて、前記半導体基板のソース
領域の一部をエッチングしてソース電極とソース領域と
のコンタクトをソース領域の側面でとったことを特徴と
する縦型電界効果トランジスタ。1. In a field effect transistor having a base region on a surface of a semiconductor substrate acting as a drain and a source region therein, a part of a source region of the semiconductor substrate is etched to form a source electrode and a source. A vertical field effect transistor characterized in that a contact with the region is made on the side surface of the source region.
にゲート酸化膜を介して形成したゲートとゲートにセル
ファライメントに形成したベース領域とその内部にゲー
トにセルファライメントに形成したソース領域とを有す
る縦型電界効果トランジスタにおいて、前記ソース領域
の一部がその深さをこえて除去されて、その部分にてベ
ース領域とソース領域の側面とにコンタクトするソース
電極を有することを特徴とする縦型電界効果トランジス
タ。2. A vertical structure having a gate formed on a surface of a semiconductor substrate acting as a drain via a gate oxide film, a base region formed on the gate in a self-alignment, and a source region formed inside the gate in the self-alignment. Type field effect transistor, characterized in that a part of the source region is removed beyond its depth, and a source electrode is in contact with the base region and the side surface of the source region at the part. Effect transistor.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP4226806A JPH0677490A (en) | 1992-08-26 | 1992-08-26 | Vertical field-effect transistor |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP4226806A JPH0677490A (en) | 1992-08-26 | 1992-08-26 | Vertical field-effect transistor |
Publications (1)
| Publication Number | Publication Date |
|---|---|
| JPH0677490A true JPH0677490A (en) | 1994-03-18 |
Family
ID=16850901
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP4226806A Pending JPH0677490A (en) | 1992-08-26 | 1992-08-26 | Vertical field-effect transistor |
Country Status (1)
| Country | Link |
|---|---|
| JP (1) | JPH0677490A (en) |
Cited By (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN105762176A (en) * | 2016-04-28 | 2016-07-13 | 电子科技大学 | Silicon carbide mosfet device and manufacturing method thereof |
-
1992
- 1992-08-26 JP JP4226806A patent/JPH0677490A/en active Pending
Cited By (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN105762176A (en) * | 2016-04-28 | 2016-07-13 | 电子科技大学 | Silicon carbide mosfet device and manufacturing method thereof |
| CN105762176B (en) * | 2016-04-28 | 2018-11-09 | 电子科技大学 | Silicon carbide MOSFET device and preparation method thereof |
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