JPS6339969Y2 - - Google Patents

Info

Publication number
JPS6339969Y2
JPS6339969Y2 JP1981191427U JP19142781U JPS6339969Y2 JP S6339969 Y2 JPS6339969 Y2 JP S6339969Y2 JP 1981191427 U JP1981191427 U JP 1981191427U JP 19142781 U JP19142781 U JP 19142781U JP S6339969 Y2 JPS6339969 Y2 JP S6339969Y2
Authority
JP
Japan
Prior art keywords
conductor layer
hybrid integrated
resin
semiconductor chip
wiring conductor
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Expired
Application number
JP1981191427U
Other languages
English (en)
Japanese (ja)
Other versions
JPS5895046U (ja
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed filed Critical
Priority to JP1981191427U priority Critical patent/JPS5895046U/ja
Publication of JPS5895046U publication Critical patent/JPS5895046U/ja
Application granted granted Critical
Publication of JPS6339969Y2 publication Critical patent/JPS6339969Y2/ja
Granted legal-status Critical Current

Links

Classifications

    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42—Wire connectors; Manufacturing methods related thereto
    • H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
    • H01L2224/4805—Shape
    • H01L2224/4809—Loop shape
    • H01L2224/48091—Arched
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42—Wire connectors; Manufacturing methods related thereto
    • H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
    • H01L2224/481—Disposition
    • H01L2224/48151—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
    • H01L2224/48221—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
    • H01L2224/48225—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation
    • H01L2224/48227—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation connecting the wire to a bond pad of the item
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42—Wire connectors; Manufacturing methods related thereto
    • H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/49—Structure, shape, material or disposition of the wire connectors after the connecting process of a plurality of wire connectors
    • H01L2224/491—Disposition
    • H01L2224/4912—Layout
    • H01L2224/49171—Fan-out arrangements
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/19—Details of hybrid assemblies other than the semiconductor or other solid state devices to be connected
    • H01L2924/191—Disposition
    • H01L2924/19101—Disposition of discrete passive components
    • H01L2924/19105—Disposition of discrete passive components in a side-by-side arrangement on a common die mounting substrate

Landscapes

  • Structures Or Materials For Encapsulating Or Coating Semiconductor Devices Or Solid State Devices (AREA)
  • Structure Of Printed Boards (AREA)
  • Wire Bonding (AREA)
JP1981191427U 1981-12-21 1981-12-21 混成集積回路 Granted JPS5895046U (ja)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP1981191427U JPS5895046U (ja) 1981-12-21 1981-12-21 混成集積回路

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP1981191427U JPS5895046U (ja) 1981-12-21 1981-12-21 混成集積回路

Publications (2)

Publication Number Publication Date
JPS5895046U JPS5895046U (ja) 1983-06-28
JPS6339969Y2 true JPS6339969Y2 (cs) 1988-10-19

Family

ID=30104888

Family Applications (1)

Application Number Title Priority Date Filing Date
JP1981191427U Granted JPS5895046U (ja) 1981-12-21 1981-12-21 混成集積回路

Country Status (1)

Country Link
JP (1) JPS5895046U (cs)

Also Published As

Publication number Publication date
JPS5895046U (ja) 1983-06-28

Similar Documents

Publication Publication Date Title
JPS6339969Y2 (cs)
JPH11233531A (ja) 電子部品の実装構造および実装方法
JP2572421Y2 (ja) チップｌｅｄ
JPH0312446B2 (cs)
JPS6038292Y2 (ja) プリント基板
JPS6153852B2 (cs)
JPH0225251Y2 (cs)
JPH0410709Y2 (cs)
JP3071438B2 (ja) 混成集積回路
JPH067275U (ja) プリント基板
JPH0238462Y2 (cs)
JPS6240442Y2 (cs)
JPH0412680Y2 (cs)
JP3002857B2 (ja) バンプ電極およびバンプ電極を持った部品
JPS5810367Y2 (ja) 混成集積回路
JPH025552Y2 (cs)
JP2523209Y2 (ja) 混成集積回路
JPS58196091A (ja) 混成集積回路の製造方法
JPS6362397A (ja) 混成集積回路の製造方法
JPH04277658A (ja) メタルコア基板
JPH0147889B2 (cs)
JPS59105395A (ja) 混成集積回路の製造方法
JPS5941888A (ja) 電子回路板及びその製造方法
JPS58102533A (ja) 混成集積回路装置の製造方法
JPS6196797A (ja) 厚膜ｈｉｃ多層基板の製造方法