JPS5895046U - 混成集積回路 - Google Patents

混成集積回路

Info

Publication number
JPS5895046U
JPS5895046U JP19142781U JP19142781U JPS5895046U JP S5895046 U JPS5895046 U JP S5895046U JP 19142781 U JP19142781 U JP 19142781U JP 19142781 U JP19142781 U JP 19142781U JP S5895046 U JPS5895046 U JP S5895046U
Authority
JP
Japan
Prior art keywords
integrated circuit
hybrid integrated
semiconductor chip
conductor layer
protective resin
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Granted
Application number
JP19142781U
Other languages
English (en)
Other versions
JPS6339969Y2 (ja
Inventor
酒井　規之
Original Assignee
ニチコン株式会社
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by ニチコン株式会社 filed Critical ニチコン株式会社
Priority to JP19142781U priority Critical patent/JPS5895046U/ja
Publication of JPS5895046U publication Critical patent/JPS5895046U/ja
Application granted granted Critical
Publication of JPS6339969Y2 publication Critical patent/JPS6339969Y2/ja
Granted legal-status Critical Current

Links

Classifications

    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42—Wire connectors; Manufacturing methods related thereto
    • H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
    • H01L2224/4805—Shape
    • H01L2224/4809—Loop shape
    • H01L2224/48091—Arched
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42—Wire connectors; Manufacturing methods related thereto
    • H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
    • H01L2224/481—Disposition
    • H01L2224/48151—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
    • H01L2224/48221—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
    • H01L2224/48225—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation
    • H01L2224/48227—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation connecting the wire to a bond pad of the item
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42—Wire connectors; Manufacturing methods related thereto
    • H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/49—Structure, shape, material or disposition of the wire connectors after the connecting process of a plurality of wire connectors
    • H01L2224/491—Disposition
    • H01L2224/4912—Layout
    • H01L2224/49171—Fan-out arrangements
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/19—Details of hybrid assemblies other than the semiconductor or other solid state devices to be connected
    • H01L2924/191—Disposition
    • H01L2924/19101—Disposition of discrete passive components
    • H01L2924/19105—Disposition of discrete passive components in a side-by-side arrangement on a common die mounting substrate

Landscapes

  • Wire Bonding (AREA)
  • Structures Or Materials For Encapsulating Or Coating Semiconductor Devices Or Solid State Devices (AREA)
  • Structure Of Printed Boards (AREA)

Abstract

(57)【要約】本公報は電子出願前の出願データであるた
め要約のデータは記録されません。

Description

【図面の簡単な説明】
第１図は従来の混成集積回路の外装樹脂を一部切除した
要部正面図、第２図は従来の混成集積回路のはんだ付は
要部の斜視図、第３図は本考案の混成集積回路の一実施
例の外装樹脂を一部切除した要部正面図、第４図は本考
案の混成集積回路の一実施例のはんだ付は要部の斜視図
である。 １：絶縁基板、２：配線導体層、４：半導体チップ、７
：保護用樹脂、９：はんだ付は用ランド部。

Claims (1)

    【実用新案登録請求の範囲】
  1. 絶縁基板上に配線導体層、半導体チップなどの厚膜回路
    パターンを形成し、半導体チップをボンディングして該
    半導体チップのボンディング部に保護用樹脂を塗布して
    なる混成集積回路において、上記半導体チップのボンデ
    ィング部と配線導体層のはんだ付は用電極ランド部間の
    配線パターンを屈曲させたことを特徴とする混成集積回
    路。
JP19142781U 1981-12-21 1981-12-21 混成集積回路 Granted JPS5895046U (ja)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP19142781U JPS5895046U (ja) 1981-12-21 1981-12-21 混成集積回路

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP19142781U JPS5895046U (ja) 1981-12-21 1981-12-21 混成集積回路

Publications (2)

Publication Number Publication Date
JPS5895046U true JPS5895046U (ja) 1983-06-28
JPS6339969Y2 JPS6339969Y2 (ja) 1988-10-19

Family

ID=30104888

Family Applications (1)

Application Number Title Priority Date Filing Date
JP19142781U Granted JPS5895046U (ja) 1981-12-21 1981-12-21 混成集積回路

Country Status (1)

Country Link
JP (1) JPS5895046U (ja)

Also Published As

Publication number Publication date
JPS6339969Y2 (ja) 1988-10-19

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