JPS6339071A - Bus control system and constitution of processing circuit - Google Patents

Abstract

PURPOSE:To prevent the contents of an internal memory from flowing to the outside by providing a gate to a processing circuit and cutting off the processing circuit from an external bus in an access mode of the internal memory. CONSTITUTION:An internal zone 100 is connected with an external zone 101 via a bus and a gate alpha is provided between an internal bus 2 and an external bus 17. The gate alpha is controlled by a CPU 1. Then both zones 100 and 101 are connected and disconnected with each other with ON/OFF of the gate alpha. When access is given to internal memories 5 and 6 in the zone 100, the gate alphais cut off to prevent the outflow of the memory contents to the outside.

Description

DETAILED DESCRIPTION OF THE INVENTION The present invention relates to a bus control system and circuit configuration for circuits such as computers. Conventional one-chip microcomputers with built-in memory cannot prevent the memory from being accessed from outside the chip or the memory contents from leaking out of the chip via the bus. In the present invention, by making it impossible to access the built-in memory from outside the chip or outside the package, it is possible to prevent the memory contents from leaking to the outside. Enables program execution and improves security. That is, the present invention provides a processing circuit with a gate β, and connects the RAN, PROM, E
The present invention relates to a bus control system and a processing circuit configuration in which an internal bus connected to a gate α is always cut off from an external bus when a memory such as a PROM or an E2PROM is accessed.

FIG. 1 shows an example of a processing circuit configuration of the present invention. The processing circuit is divided into an internal zone (100) and an external zone (101), and the internal zone (100) includes a CPU (1).
, internal bus (2), gate α (3), gate β (4),
Internal ROM (5), internal RAM (6), address decoder (8), AND gate (11), flip-flop (12), control lines (13), (14), (15), etc. are built-in.

(100) is constructed so that internal bus wiring, IC terminals, etc. are not exposed so as not to be accessed from the outside world.

For this purpose, converting the entire circuit into a single-chip IC or enclosing it in a hard case is suitable.

The internal bus (2) is connected to the CPU (1), an internal ROM (5) via gate β (4), an internal RAM (6) via gate β (4), and gate α (3). Furthermore, a buffer memory and an arithmetic processor (7) are connected.

Internal bus (2) and external bus (17) are connected to gate α (3)
Intermittent and connected connections are made by opening and closing. Connections between the internal RAM (6) and internal ROMs (5) and the internal bus (2) are made by opening and closing the gate β (4). Gate α (3) and gate β (4) are opened and closed by control inputs to each gate from control lines (13) and (14). When β is closed, that is, connected, α is open, that is, connected. Configure to be in an intermittent state. In the illustrated example, one flip-flop (12)
When the CPU (1) issues a signal IOR or IOW for gate opening/closing by executing a command, the address decoder (8) confirms this and sends a select signal (9).
The AND gate (11) in conjunction with (10) triggers the flip-flop (12), inverts the polarity of the outputs Q and Q, and simultaneously connects both outputs to the control lines (13) and (14).
input into α and β via . In addition to this, two sets of address decoders and flip-flops can be used to
The timing of opening and closing may be performed independently. In either case, the gate α is configured so that it is always open when the gate β is closed.

In the external zone (101), the external bus (17) is connected to the gate α (3), external ROM (18), external RAM (19),
Connect the I/O interface (20), device interface (21), etc. No security consideration is required for wiring, terminals, etc. in the external zone. On the other hand, to ensure security, the internal zone (100) is either stored in a single chip as shown in Figure 2 [a], or assembled on a single board and then placed in a hard case as shown in Figure 2 [b]. Enclose in. Furthermore, as shown in Fig. 2 (c), a multi-board configuration may be used, or a built-in device may be used to explain the circuit or prevent the ROM from being removed by exposing the terminals and wiring by drilling holes from the outside, or by partially cutting off the enclosed solid. IC
By adjusting the direction and position of the wire, the angle of the wires, and the weight relationship, it is possible to make the wire more likely to collapse during an unauthorized autopsy. These one-chip or one-packaged inner zones (100) are
External zone (101) of another board as shown in Figure 2 [d]
Use in combination with

When executing a confidential program, first give an I/O command etc. to make the CPU (1) output an IOR or IOW signal, and the address decoder (8) acknowledges and triggers a flip-flop, causing the control line (13) to go low. The gate α (3) is opened to disconnect the internal bus (2) from the external bus (17). On the other hand, the control line (14) is set to H, gate β (4) is closed, and the internal memory (5) (6) and internal bus (
2), thus realizing a closed internal zone (100). After this, the execution procedure is configured so that α is not connected to connect the internal bus and the external bus while the contents of the internal memory remain in the buffer memory (7).

This can be achieved, for example, by resetting the buffer memory when executing an I/O command instructing α connection.

A 3-state gate or the like is used for the gate β.

Note that by providing a separate buffer memory (24) that is not reset when the α connection instruction command is executed and storing processing results, etc., it is possible to transmit information between the internal zone and the external zone. It is also possible to employ a chip-on-board type element (23).

[Brief explanation of the drawing]

FIG. 1 shows an example of the circuit configuration of the present invention, and FIG. 2 shows an example of the configuration of the inner zone of the present invention, and an example of a combination of the inner zone and the outer zone.

Claims (1)

[Claims] A bus control system and a processing circuit configuration in which a gate β is provided among the gates shown in the text, and the internal bus connected to α is always cut off from the external bus when the memory connected to β is accessed.