JPH05135188A - Microcomputer - Google Patents

Abstract

PURPOSE:To make an observation from outside possible by outputting data, which are transferred between internal resources, to the outside. CONSTITUTION:When a CPU 2 accesses an internal RAM 4, an internal register 5a, etc., and data transfer is performed in the microcomputer 1 through an internal bus 3, a buffer control means 10 places an input/output buffer 91 for a top-surface terminal in an output state and outputs the data transferred inside from the top surface terminal 6 to an ICE 12, and the transfer data can be observed from outside by the ICE 12.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a microcomputer comprising a piggyback type semiconductor integrated circuit having a package data output terminal provided on the upper surface of the package.

[0002]

2. Description of the Related Art FIG. 1 is a block diagram showing the configuration of a conventional piggyback microcomputer, in which 1 is a microcomputer including a semiconductor integrated circuit.

The upper surface terminal 6 provided on the upper surface of the package of the microcomputer 1 supports the debugging by making it possible to externally observe the data transferred according to the operation of the microcomputer 1 and an ICE (In Circuit Emulato).
r) 12 and the side terminal 8 is connected to an external bus 11 for transferring data between the microcomputer 1 and the outside.

The internal resources of the microcomputer 1, such as the CPU 2, the internal RAM 4, the internal register 5a of the internal I / O circuit 5, etc., are connected to the internal bus 3, respectively. Is transferred.

The internal bus 3 is connected to an input / output buffer 9 for temporarily storing data input / output via the above-mentioned upper surface terminals 6 and side surface terminals 8. The input / output buffer 9 is controlled by the buffer control means 10. Opening and closing is controlled.

When the CPU 2 accesses an external memory or the like, the buffer control means 10 opens the input / output buffer 9, and the data of the internal bus 3 is transferred from the side surface terminal 8 to the external bus 11 via the input / output buffer 9 Data on the bus 11 is transferred from the side terminal 8 to the internal bus 3. At that time, the side terminal 8
The input / output data of is output from the upper terminal 6 to the ICE 12.

On the other hand, when the CPU 2 accesses the internal resource, the buffer control means 10 closes the input / output buffer 9 and the data is transferred via the internal bus 3. Therefore, the data transferred between the internal resources via the internal bus 3 is not output from the upper surface terminal 6.

FIG. 2 shows the internal bus 3, side terminals 8 and top terminal 6 when the CPU 2 reads / writes the internal memory such as the external memory or the internal RAM 4 and the internal register 5a.
3 is a timing chart showing respective data input / output states. As is apparent from the figure, when the CPU 2 reads / writes to the internal memory, no data is output from the upper surface terminal 6.

[0009]

In the conventional microcomputer having the above-mentioned configuration, the data transferred between the internal resources of the microcomputer is not output from the upper surface terminal, and the transferred data inside cannot be observed outside. However, there is a problem that the operation of the microcomputer cannot be accurately grasped.

The present invention has been made to solve such a problem, and provides a microcomputer capable of accurately grasping its operation by outputting data transferred between internal resources to the outside. To aim.

[0011]

A microcomputer according to the present invention is characterized in that data transferred between internal resources is output to the outside so that transfer data inside can be observed outside.

Further, the microcomputer according to the present invention is characterized in that the data transferred to and from the external resource is output to the outside so that it can be observed outside.

[0013]

When the data is transferred between the internal resources, the microcomputer according to the present invention outputs the transferred data from the observation data output terminal to the outside so that the observation can be performed outside.

Further, when data is transferred to or from an external resource, the microcomputer according to the present invention inputs / outputs this transferred data and outputs it from the observation data output terminal to the outside for observation outside. It is possible.

[0015]

The present invention will be described below with reference to the drawings showing the embodiments thereof. FIG. 3 is a block diagram showing the configuration of a piggyback microcomputer according to the present invention, in which 1 is a microcomputer including a semiconductor integrated circuit.

The upper surface terminal 6 provided on the upper surface of the package of the microcomputer 1 is connected to the ICE 12, and the side surface terminal 8 is connected to the external bus 11 for transferring data between the microcomputer 1 and the outside.

Internal resources of the microcomputer 1, such as the CPU 2, the internal RAM 4, the internal register 5a of the internal I / O circuit 5, etc., are connected to the internal bus 3, respectively. Is transferred.

The internal bus 3 is connected to the above-mentioned upper surface terminals 6
An upper surface terminal input / output buffer 91 for temporarily storing input / output data for the ICE 12 and a side surface terminal input / output buffer 92 for temporarily storing input / output data for the external bus 11 via the side surface terminal 8 are connected. I / O buffer
91 and the side terminal input / output buffer 92 are buffer control means.
Its opening and closing is controlled by 10.

When the CPU 2 accesses an external memory or the like, the buffer control means 10 operates the side terminal input / output buffer 92.
And the upper surface terminal input / output buffer 91 is opened, and the data of the internal bus 3 is transferred from the side surface terminal 8 to the external bus 11 and the data of the external bus 11 is transferred from the side surface terminal 8 to the inside through the side surface terminal input / output buffer 92 Transferred to bus 3. that time,
Input / output data of the side surface terminal 8 is output from the upper surface terminal 6 to the ICE 12 from the internal bus 3 via the upper surface terminal input / output buffer 91.

On the other hand, when the CPU 2 accesses the internal resource, the buffer control means 10 causes the side terminal input / output buffer 92.
On the other hand, the input / output buffer 91 for the upper surface terminal is opened to the output state, and the data transferred between the internal resources via the internal bus 3 is output from the upper surface terminal 6 to the ICE 12.

When the CPU 2 accesses the memory in the ICE 12, the upper surface terminal input / output buffer 91 is opened to the input state by the buffer control means 10.

FIG. 4 shows the internal bus 3, the side terminals 8 and the top terminals 6 when the CPU 2 reads / writes the internal memory such as the external memory or the internal RAM 4 and the internal register 5a.
3 is a timing chart showing respective data input / output states. As is clear from the figure, even when the CPU 2 reads / writes to the internal memory, data is output from the upper surface terminal 6.

[0023]

As described above, the microcomputer according to the present invention outputs the data transferred with the external resource and the data transferred with the internal resource to the outside so that the microcomputer can observe the data. It has an excellent effect that the operation of can be grasped accurately.

[Brief description of drawings]

FIG. 1 is a block diagram showing a configuration of a conventional piggyback microcomputer.

FIG. 2 is a timing chart showing a data input / output state in a conventional microcomputer.

FIG. 3 is a block diagram showing a configuration of a piggyback microcomputer according to the present invention.

FIG. 4 is a timing chart showing a data input / output state in the microcomputer according to the present invention.

[Explanation of symbols]

 1 Microcomputer 2 CPU 3 Internal Bus 4 Internal RAM 5 Internal I / O Circuit 5a Internal Register 6 Top Terminal 8 Side Terminal 10 Buffer Control Means 11 External Bus 12 ICE 91 Top Terminal Input / Output Buffer 92 Side Terminal Input / Output Buffer

Claims (2)

[Claims] 1. A microcomputer provided with a terminal for outputting the data to the outside so that the data transferred according to the operation can be observed outside, A microcomputer provided with a circuit for outputting from a terminal to the outside. 2. The micro according to claim 1, further comprising an input / output terminal for inputting / outputting data transferred to / from an external resource, and means for outputting data input / output by the input / output terminal from the terminal. Computer.