JPH02153448A - Semiconductor integrated circuit device - Google Patents

Abstract

PURPOSE:To efficiently perform an input/output processing by performing the input/output processing between a control function part and an external device based on address information generated by the control function part. CONSTITUTION:Control information transferred between an LSI external device and a buffer part 8 in an input/output processor 4 is stored in advance in the address information5 generated by the control function part 2. Therefore, an interface processing with the outside of an LSI can automatically be performed by executing an instruction to input/output data by designating a specific address via the input/output processor 4. In such a way, for example, the CPU of the control function part 2 is sufficiently provided with capacity of address arithmetic operation, etc., and it can fully be utilized even in the input/output processing.

Description

[Detailed Description of the Invention] [Table of Contents] Overview Industrial Field of Application Conventional Technology Problems to be Solved by the Invention Means for Solving the Problems Working Examples Explanation of the Principle of the Invention (Figure 1) Part of the Invention Embodiments (Figures 2 to 5) Effects of the invention [Summary] Regarding a semiconductor integrated circuit device, communication between a certain integrated circuit device (hereinafter referred to as an LSI) and a plurality of external LSIs can be performed mainly in a parallel manner. The purpose of the present invention is to provide a semiconductor integrated circuit device that can perform input/output processing efficiently and that holds predetermined address information, outputs address signals based on the address information, and inputs data signals. or an input/output processing device to which the address signal is input, the data signal is input or output, and the data signal is exchanged between the control function unit and a predetermined external device; , wherein the input/output processing device includes a terminal section that can be input to or output from an external device, and a buffer section that decodes an address signal input from the control function section. and the buffer section that processes or stores the data signal or the signal input from the terminal section, and includes an external device and the buffer section in the address information generated by the control function section. The address of the external device of the data signal exchanged between the sections is held in advance, and input/output processing between the control function section and the external device is performed based on the address information.

[Industrial application field]

The present invention relates to a semiconductor integrated circuit device, and more particularly to an improvement of an LSI input/output processing device having a data processing function such as a microcomputer.

In recent years, with the spread of LSIs, especially microcomputers capable of various types of processing, and related LSIs, and their increasing degree of integration, there is a need for high-speed and economical methods for exchanging data processed by these LSIs between LSIs. It's starting to look like this.

[Conventional technology]

Conventional data exchange between LSIs can be roughly divided into two types: parallel and serial. In the parallel method, data is usually exchanged via a temporary storage unit called a boat, but in this case, there are two methods: setting only the data and exchanging and processing it using software, and one method that sends a signal to notify the other party of the data set signal. A method is adopted in which communication occurs between two LSIs.

On the other hand, there are various serial communication methods, but all of them use data only or both data and clock to effectively utilize the limited terminals of LSI.
Exchanges between LSIs are carried out in about 10 minutes.

[Problem to be solved by the invention]

However, in such conventional semiconductor integrated circuit devices, the serial method allows various types of processing to be performed freely.
Although it makes effective use of LSI terminals, as the processing speed inside the LSI becomes faster, the slow transfer speed becomes a problem, especially when the processing unit inside the LSI becomes 16 bits or 3 bits.
When it comes to 2 bits, the imbalance becomes a problem.

On the other hand, although the parallel system can perform high-speed processing to some extent and is compatible with internal processing functions, the conventional system has the drawback that communication between multiple LSIs cannot be performed efficiently.

Therefore, the present invention enables communication between a certain LSI and a plurality of external LSts to be performed primarily in parallel (not necessarily completely simultaneously), and to efficiently perform input/output processing. The purpose is to provide an LSI semiconductor integrated circuit device.

[Means for Solving the Problems] In order to achieve the above object, a semiconductor integrated circuit device according to the present invention holds predetermined address information, outputs an address signal based on the address information, and inputs or outputs a data signal. an input/output processing device to which the address signal is input and the data signal is input or output, and which transmits and receives data signals between the control function unit and a predetermined external device; , wherein the input/output processing device includes a terminal section that can be input to or output from an external device, and a buffer section that decodes an address signal input from the control function section. and the buffer section that processes or stores the data signal or the signal input from the terminal section,
The address information of the external device of the data signal exchanged between the external device and the buffer section is held in advance in the address information generated by the control function section, and the address of the external device is stored in advance in the address information generated by the control function section and the external device. A semiconductor integrated circuit device is provided, characterized in that input/output processing between devices is performed.

[Effect]

In the present invention, control information exchanged between an LSI external device and a buffer section in the input/output processing device is stored in advance in the address information generated by the control function section.

Therefore, by executing an instruction to input/output data by pointing to a specific address, interface processing with the outside of the LSI is automatically and efficiently performed through the input/output processing device. In this case, the CPU of the AM control section, for example, has sufficient ability to perform address calculations and the like, and this ability can be fully utilized for input/output processing.

〔Example〕

Hereinafter, the present invention will be explained based on the drawings.

Figure 1 is a diagram for explaining the principle of a semiconductor integrated circuit device according to the present invention. First, the configuration will be explained. In FIG. 1, 1 is an LSI (semiconductor integrated circuit device);
The SII includes a functional processing unit 2 such as a CPU that outputs address signals (hereinafter simply referred to as addresses) and inputs and outputs data signals (hereinafter simply referred to as data), and internal hardware 3.
, an input/output processing device 4 to which addresses are input and input/output data, and a bus 5.6 that carries addresses and data, and the input/output processing device 4 receives and decodes predetermined address signals. and a control circuit 7 that performs control;
The input/output processing device 4 is connected to the data signal in the LSII.
A storage/processing unit (buffer unit) 8 under the control of the LSI
It is composed of an external terminal section (terminal section) 9 and a bus 10 that is connected to the LSI external terminal section 9 and communicates with the outside of the LSI. Here, the internal hardware 3 is often connected to the addresses and data input/output through the bus 5.6 as shown in the figure, but the internal hardware 3 is not necessarily essential to the present invention. . The input/output processing device 4 is a device that performs input, output, or input/output with the outside of the LSII via the LSI external terminal section 9, and may have a section that outputs address information for addressing the outside of the LSI to the LSI external terminal section 9. However, in this case, in order to indicate that it may be generated from one or both of the storage/processing section (buffer section) 8 or the control section of the control circuit 7, the broken line in the figure It's tied. The terminal section 9 is generally indicated by the usual input/output symbol, but is a mixture of terminals for either input, output or input/output functions.

Further, since LSI data and addresses often physically share the same signal line, the data and addresses are indicated by broken lines to include this case. Similar to the above, the data input/output signal indicates that it has any of the functions of input, output, and input/output.

A major feature of the present invention is that control information for the input/output processing device 4 is included in the address information generated by the control function section 2.

With this configuration, it is possible to execute an instruction that points to a specific address and outputs data, and the LS
Interface processing with the outside can be performed automatically and efficiently through the input/output processing device 4. On the other hand, the CPU, for example, has sufficient capabilities such as address calculation, and can fully utilize this capability for input/output processing. Further, since addressing is provided not only for specific instructions but also for a wide range of instructions, various instructions can be used.

double U An actual device based on the above principle will be described as an example.

2 to 5 are diagrams showing an embodiment of the semiconductor integrated circuit device according to the present invention, FIG. 2 is an overall configuration diagram, and FIG. 3 is an LS
FIG. 4 is a detailed block diagram of the input/output processing device 4.

In explaining this embodiment, the same components as those in the principle explanation shown in FIG. 1 are given the same reference numerals, and the explanation thereof will be omitted.

First, the configuration will be explained. In Figure 2, 11.12 is an external LSI that exchanges data with the LSII.
SI 111 and LSI 212 are, for example, LSIs that have memory or a memory function and also perform dedicated control functions.
is used. In the figure, 13 is a CPU, and CPU1
3 handles 20-bit addresses and 16-bit data, and uses ROM 14 and RAM 15 to process control firmware. The LSII also includes a timer 16 and a serial interface 17, and executes various control functions.

In this embodiment, data output to the outside of the LSI is performed in the following two ways by taking advantage of the functionality of the CPU 13 whose addressing ability has been improved to 20 bits, and by taking advantage of the fact that in a single-chip microcomputer, not all RAM is actually used. Let's take an example of an input/output processing device in which this method is used.

(1) AND the data written to the input/output processing device 4 and the contents of a predetermined address of the external device (LSI) and store the result at the original address.

(2) The data written in the input/output processing device 4 is ORed with the contents of a predetermined address in the external device (LSI) and stored in a predetermined memory.

(3) Exclusive OR (EOR) of the data written to the input/output processing device 4 and the contents of the specified location of the external device
ve OR) and store it at the original address.

(4) Forcibly write the data written in the input/output processing device 4 to a predetermined location of the external device (LSI).

Here, the address seen from the CPU 13 is shown in FIG. 3, and the address actually used inside the LSI is 0.
00001 (-OFFFFH. Therefore, if a write is performed to the input/output processing device 4 pointing to an address of 100OOH or more, the input/output processing device 4
works as follows.

RorororoxxxxxxxxxxxxxxxxxLSI#
1. As mentioned above, #2 is an LSI that has a memory or memory function and also performs a dedicated control function, and it efficiently performs the above four types of operations by writing specified data to the corresponding address based on the above configuration. can be executed.

FIG. 4 is an internal configuration diagram of the input/output processing device 4 showing the above operating functions. In the figure, 21 is an internal bus that carries 16-bit addresses and data, 22 is the upper 4 bits of the address and timing signals, 23 is the data latch, 24 is the address latch, and 25 is the address decoding and sequence using the above 4 bits of the address. A signal input to a control unit 27 that performs control, 26 is a multiplexer, 27 is a control unit that performs address decoding and sequence control, 28 is AND,
OR, EOR.

Arithmetic circuit having through modes, 29 is arithmetic circuit 2
8 a control signal, 30 a signal bus with the outside of the LSI, 31 an LSI select signal, 32 a Read/Write signal, 33 an address output strobe signal, and 34 an address input strobe signal.

In this embodiment, addresses and data are inputted on the internal bus 21 inside the LSI in a time-division manner, and the upper 4 bits of the address and timing signals are inputted independently as shown by 22 in the figure. However, of course, these may be cases in which the address and data are separated.

Next, the effect will be explained.

First, when an address and data are input from the function processing unit 2 to the input/output processing device 4, the data and address are latched by the data latch 23 and the address latch 24, and the upper 4 bits of the address latch 24 are decoded and the next The control sequence in which the input/output processing device 4 should operate is given to the control section 27 through the signal line 25.

Then, the lower 16 bits of the address latch 24 are outputted to the outside of the LSI via the signal bus 30 through the multiplexer 26 and the arithmetic circuit 28, and at this time, the address output timing signal (Read/Write signal 32, address output strobe signal 33) and LSI select signal 3
1, LSI #1. Indicates one of the predetermined addresses #2. As a result, the address input strobe 34 becomes a strobe and the contents of the predetermined address enter the arithmetic circuit 28 through the signal bus 30 with the outside of the LSI.

At this time, the contents of the data latch 23 are transferred to the multiplexer 26.
input simultaneously through, predetermined AND, OR.

After performing any of the EOR operations, writing is performed again using strobe signals 32 and 33 via the signal bus 30 with the outside of the LSI.

For the above series of operation flow, set address F8 of LSI #2 to 000.
The timing chart in FIG. 4 shows the result obtained by ORing with 2H (setting the first bit). Here, L
Although the signal bus 30 with respect to the outside of the SI is designed for 16-bit input/output, it goes without saying that 8-bit input/output may be performed twice in order to reduce the number of terminals.

In this way, by placing data in a fixed location when communicating with devices external to the LSI, complex operations can be realized with simple hardware, making use of the powerful addressability of the CPU, and input/output on the CPU side. This has the advantage of reducing the processing burden.

〔Effect of the invention〕

According to the present invention, communication with a plurality of external LSIs can be performed primarily in parallel, and input/output processing can be performed efficiently.

[Brief explanation of the drawing]

FIG. 1 is an explanatory diagram of the principle of a semiconductor integrated circuit device according to the present invention, FIGS. 2 to 5 are diagrams showing an embodiment of the semiconductor integrated circuit device according to the present invention, and FIG. 2 is an overall configuration diagram thereof. 3 is an address map of the LSI, FIG. 4 is a block diagram of the input/output processing device 4, and FIG. 5 is a timing chart showing its operation flow. 1... LSI (semiconductor integrated circuit device), 2...
...Function processing unit, 3...Internal hardware, 4...Input/output processing device, 5.6.10...Bus, 7...・Control circuit, 8... Storage/processing section (buffer section), 9...
...LSI external terminal section (terminal section), 11...
LSI$1. 12...LSI$2. 13...CPU. 14...ROM. 15...RAM. 16...Timer, 17...Serial interface, 21...
...Internal bus connecting 16-bit RAM and data, 22...Address upper 4 bits and timing signal, 23...De-clutch, 24...Address Latch, 25... Signal input to control unit 27, 26.
...Multiplexer, 27...Control unit that performs decoding sequence control using the upper 4 bits of the address, 28...Arithmetic circuit having AND, OR, EOR, and through modes, 29... Control signal of the arithmetic circuit 28, 30...
...Signal bus with external LSI, 31...LS
I select signal, 32-- Read/Wri
te signal, 33...address output strobe signal, 34...address input strobe signal. 11: LSI #1 i2: LsI #2 13: cPU - LSI address map diagram of the embodiment $ 3 Figure

Claims (1)

[Claims] A control function section that holds predetermined address information, outputs an address signal based on the address information, and inputs or outputs a data signal; A semiconductor integrated circuit device comprising an input/output processing device into which signals are input or output and which transmits and receives data signals between the control function section and a predetermined external device, the input/output processing device comprising: a terminal section that can be input to or output from an external device; a control circuit that decodes the address signal input from the control function section and controls the buffer section; and a control circuit that controls the data signal or the signal input from the terminal section. the buffer section for processing or storing the data, and the address of the external device of the data signal exchanged between the external device and the buffer section is held in advance in the address information generated by the control function section. Also, a semiconductor integrated circuit device, wherein input/output processing between the control function section and an external device is performed based on the address information.