JPS6050934A - Test facilitating circuit - Google Patents

Test facilitating circuit

Info

Publication number
JPS6050934A
JPS6050934A JP58157199A JP15719983A JPS6050934A JP S6050934 A JPS6050934 A JP S6050934A JP 58157199 A JP58157199 A JP 58157199A JP 15719983 A JP15719983 A JP 15719983A JP S6050934 A JPS6050934 A JP S6050934A
Authority
JP
Japan
Prior art keywords
signal
test
input
signals
test mode
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
JP58157199A
Other languages
Japanese (ja)
Inventor
Takumi Tsubouchi
坪内　工
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Toshiba Corp
Original Assignee
Toshiba Corp
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Toshiba Corp filed Critical Toshiba Corp
Priority to JP58157199A priority Critical patent/JPS6050934A/en
Publication of JPS6050934A publication Critical patent/JPS6050934A/en
Pending legal-status Critical Current

Links

Classifications

    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L22/00—Testing or measuring during manufacture or treatment; Reliability measurements, i.e. testing of parts without further processing to modify the parts as such; Structural arrangements therefor

Landscapes

  • Engineering & Computer Science (AREA)
  • Manufacturing & Machinery (AREA)
  • Computer Hardware Design (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Power Engineering (AREA)
  • Testing Or Measuring Of Semiconductors Or The Like (AREA)
  • Techniques For Improving Reliability Of Storages (AREA)
  • Semiconductor Integrated Circuits (AREA)
  • For Increasing The Reliability Of Semiconductor Memories (AREA)
  • Testing Of Individual Semiconductor Devices (AREA)
  • Tests Of Electronic Circuits (AREA)

Abstract

PURPOSE:To contrive the reduction in the number of test controlling pins by a method wherein an LSI is provided with a test mode input pin and a mode switching circuit, so as to utilize a signal input pin also for the input of a test control signal by mode switching. CONSTITUTION:In the normal case, the test mode signal fed to the test mode signal input pin 2 is kept false, when the signals obtained via system signal input pins 5a and 5b are used as system input signals 6a and 8c as they are. At this time, there are no influences on the test control signals 8a and 8b in the presence of AND gates 7A and 7B, and the LSI performs the original action. Next, the signal 4a is turned true on the test mode, when the signals from the pins 5a and 5b can be directly changed into the signals 8a and 8b. During this test control, there are the cases where the input is preferable in being transmitted to the system or not preferable, however, in the latter case, it is kept gated by means of the AND gate 7c as the system input signal 8c.

Description

【発明の詳細な説明】 〔発明の技術分野〕 本発明はＴ、　Ｓ　Ｈに内蔵されたテスト容易化回路に
関する。DETAILED DESCRIPTION OF THE INVENTION [Technical Field of the Invention] The present invention relates to a test facilitation circuit built into a T, SH.

〔発明の技術的背景〕[Technical background of the invention]

最近、半導体技術の進歩に伴って各種数多くのＬＳＩが
開発されるようになってきたが、大規模なＬＳＩでは検
査が非常に大変であるため、本来の機能に加えて検査の
容易性を向上させるためテスト機能を持つものが多い。Recently, with the advancement of semiconductor technology, a large number of various LSIs have been developed, but since testing large-scale LSIs is extremely difficult, we have improved the ease of testing in addition to the original functions. Many of them have test functions to ensure that

［背景技術の問題点〕 高度なテスト機能を実現するためには通常、多数のテス
ト制御信号が必要であるからＬＳＩにはシステム本来の
入力用ビンとは別に、数多くのテスト制御専用の入力ピ
ンを設ける必要があった。[Problems with the background technology] Since a large number of test control signals are usually required to realize advanced test functions, LSIs have a large number of input pins dedicated to test control, in addition to the system's original input bins. It was necessary to set up

しかし多くの場合Ｌ　Ｓ　Ｉのパッケージ上の制限から
そうたくさんのテスト制御用ビンを持てないという問題
があった。However, in many cases, there is a problem in that it is not possible to have so many test control bins due to limitations on the LSI package.

〔発明の目的〕[Purpose of the invention]

本発明は以上に鑑み、少ないテストピンで数多くのテス
ト制御信号を取扱うことが出来るような手段を提供する
ことを目的とする。In view of the above, an object of the present invention is to provide means that can handle a large number of test control signals with a small number of test pins.

〔発明の概要〕[Summary of the invention]

本発明ではＬＳＩにテストモード入力ピンとモード切換
回路とを設はモード切換えにより信号入力ビンをテスト
制御信号の入力にも利用できるようにしてテスト制御用
ピンの減少をはかったものである。In the present invention, the LSI is provided with a test mode input pin and a mode switching circuit so that the signal input bin can also be used for inputting test control signals by mode switching, thereby reducing the number of test control pins.

〔発明の実施例〕[Embodiments of the invention]

第１図は本発明の一実施例の主要部を示した回路図であ
る。同図に於て、（１）はＬＳＩの内外を区別する線で
その左側が外部、右側が内部を示している。（２）はテ
ストモードであるか否かを示す信号が伝播するテストモ
ード信号入力ピン、（３）はインバータ、（４ａ）はテ
ストモード信号、（４ｂ）は反転テストモード信号、（
５ａ）〜（５ｂ）はシステム信号入力ピン、（６ａ）〜
（６ｂ）はシステム入力信号、（７Ａ）はシステム入力
信号（６ａ）とテストモード信号（４ａ）とを入力して
テスト制御信号（８ａ）を出力するアントゲ−）　Ａ、
　（７Ｂ）はシステム入力信号（６ｂ）とテストモード
信号（４ａ）とを入力してテスト制御信号（８ｂ）を出
力するアントゲ−）Ｂ、（７Ｃ）はシステム入力信号（
６ｂ）と反転テストモード信号（４ｂ）とを入力してシ
ステム入力信号（８ｃ）を出力するアンドゲートＣであ
る。FIG. 1 is a circuit diagram showing the main parts of an embodiment of the present invention. In the figure, (1) is a line that distinguishes the inside and outside of the LSI, with the left side showing the outside and the right side showing the inside. (2) is a test mode signal input pin through which a signal indicating whether or not it is in test mode is propagated, (3) is an inverter, (4a) is a test mode signal, (4b) is an inverted test mode signal, (
5a) to (5b) are system signal input pins, (6a) to
(6b) is a system input signal, (7A) is an anime game that inputs the system input signal (6a) and the test mode signal (4a) and outputs the test control signal (8a)) A.
(7B) is an analog game that inputs the system input signal (6b) and the test mode signal (4a) and outputs the test control signal (8b), and (7C) is the system input signal (
6b) and an inverted test mode signal (4b), and outputs a system input signal (8c).

次に第１図の機能動作を説明する。通常の場合はテスト
モード信号（４ａ）を偽にしておく。するとシステム信
号入カビ／（５Ｒ）　（５ｂ）を介して得られる信号は
そのままシステム入力信号（６ａ）　（８ｃ）として使
われる。このときゲート（７Ａ）（７Ｂ）によりテスト
制御信号（８ａ）　（８ｂ）への影響はなく、Ｌ　ＳＩ
は本来の動作をする。次にテストモードではテストモー
ド信号を真にする。するとシステム信号入力ピン（ｓａ
）　（５ｂ’）からの信号を直接テスト制御信号（８ａ
）　（８ｂ）にすることが出来る。このテスト制御中、
入力がシステム入力に伝わってもよい場合とよくない場
合とがあるが後者の場合はシステム入力信号（８ｃ）の
ようにアンドゲートＣ（７Ｃ）でゲートしておくように
する。Next, the functional operation of FIG. 1 will be explained. In normal cases, the test mode signal (4a) is set to false. Then, the signals obtained through the system signal inputs (5R) (5b) are used as they are as system input signals (6a) (8c). At this time, the test control signals (8a) (8b) are not affected by the gates (7A) (7B), and the LSI
behaves as it should. Next, in test mode, the test mode signal is set to true. Then the system signal input pin (sa
) (5b') directly test control signal (8a
) (8b). During this test control,
There are cases in which the input may be transmitted to the system input, and cases in which it is not. In the latter case, it is gated with an AND gate C (7C) like the system input signal (8c).

〔発明の効果〕〔Effect of the invention〕

本発明は以上のようになるものであって、テストモード
入力用のピンを１本追加することにより外部から直接に
多数のテスト制御信号を入力出来るようになる効果の得
られるものである。The present invention is as described above, and by adding one pin for test mode input, it is possible to directly input a large number of test control signals from the outside.

【図面の簡単な説明】[Brief explanation of the drawing]

第１図は本発明の一実施例の主要部を示す回路図である
。 ２：テストモード信号入力ピン、 ４ａ：テストモード信号、 ５ａ、５ｂ　ニジステム信号入力ピン、６ａ、６ｂシス
テム入力信号、 ７Ａ、７Ｂ、７Ｃ：アンドゲート、 ８ａ、８ｂ　：テスト制御信号。 代理人　弁理士　井　上　−男 ＠１図FIG. 1 is a circuit diagram showing the main parts of an embodiment of the present invention. 2: Test mode signal input pin, 4a: Test mode signal, 5a, 5b System signal input pin, 6a, 6b system input signal, 7A, 7B, 7C: AND gate, 8a, 8b: Test control signal. Agent Patent Attorney Inoue - Male @1 diagram

Claims (1)

【特許請求の範囲】[Claims] 入力信号が伝播する入力ビンの他に、テストモードであ
ることを示す信号が伝播する唯１本のテストビンと、該
テストピン及び上記入力ピンを介して伝播する信号を入
力とするゲート回路を備え、該ゲート回路により上記テ
ストピンを介して伝播する信号がノーマルモードを示し
ていたとき上記入力ピンを本来のシステム入力用として
、テストモードを示していたとき、テスト制御信号伝播
用として使用することな特徴とするＬＳＩ内蔵のテスト
容易化回路。In addition to the input bin through which the input signal is propagated, there is only one test bin through which a signal indicating the test mode is propagated, and a gate circuit whose input is the signal propagated through the test pin and the input pin. When the signal propagated through the test pin by the gate circuit indicates the normal mode, the input pin is used for the original system input, and when the signal indicates the test mode, the input pin is used for propagating the test control signal. A test-facilitating circuit with built-in LSI features.
JP58157199A 1983-08-30 1983-08-30 Test facilitating circuit Pending JPS6050934A (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP58157199A JPS6050934A (en) 1983-08-30 1983-08-30 Test facilitating circuit

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP58157199A JPS6050934A (en) 1983-08-30 1983-08-30 Test facilitating circuit

Publications (1)

Publication Number Publication Date
JPS6050934A true JPS6050934A (en) 1985-03-22

Family

ID=15644364

Family Applications (1)

Application Number Title Priority Date Filing Date
JP58157199A Pending JPS6050934A (en) 1983-08-30 1983-08-30 Test facilitating circuit

Country Status (1)

Country Link
JP (1) JPS6050934A (en)

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US9696289B2 (en) 2012-05-15 2017-07-04 Robert Bosch Gmbh Method and control unit for compensating for a voltage offset of a two-point lambda sensor

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US9696289B2 (en) 2012-05-15 2017-07-04 Robert Bosch Gmbh Method and control unit for compensating for a voltage offset of a two-point lambda sensor

Similar Documents

Publication Publication Date Title
JPH05181982A (en) Large-scale integrated circuit device
JPS6050934A (en) Test facilitating circuit
JPH04248483A (en) Semiconductor integrated circuit
JPS55157022A (en) Output circuit for microcomputer
JPS5694596A (en) Memory control system
JP2935710B2 (en) Test equipment for processor integrated circuit devices
JPS54158831A (en) Data processor
JPH02263222A (en) Reset input system for digital signal processor
JPH01135224A (en) Latch circuit
JPH0483414A (en) Latch circuit
JPS62159256A (en) Memory data checking system
JPS6276756A (en) Semiconductor device with self-inspecting circuit
JPS5973777A (en) Method for testing lsi mounted to substrate
JPH03118652A (en) Integrated circuit
JPH0346350A (en) Semiconductor integrated circuit device
JPH02163840A (en) Single chip microcomputer
JPH04103143A (en) Semiconductor integrated circuit
JPH0568752B2 (en)
JPS6214866B2 (en)
JPH04317139A (en) In-circuit emulator device
JPS55153453A (en) Communication control unit
JPH02100716A (en) Arithmetic circuit
JPS6093362A (en) Testing system of unit with integrated circuit element mounted
JPS61184636A (en) Arithmetic circuit
JPH0561817A (en) Semiconductor device and electronic equipment