JPS55153453A - Communication control unit - Google Patents
Communication control unitInfo
- Publication number
- JPS55153453A JPS55153453A JP6093779A JP6093779A JPS55153453A JP S55153453 A JPS55153453 A JP S55153453A JP 6093779 A JP6093779 A JP 6093779A JP 6093779 A JP6093779 A JP 6093779A JP S55153453 A JPS55153453 A JP S55153453A
- Authority
- JP
- Japan
- Prior art keywords
- circuit
- data
- fed
- unit
- flag
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Granted
Links
Classifications
-
- H—ELECTRICITY
- H04—ELECTRIC COMMUNICATION TECHNIQUE
- H04L—TRANSMISSION OF DIGITAL INFORMATION, e.g. TELEGRAPHIC COMMUNICATION
- H04L1/00—Arrangements for detecting or preventing errors in the information received
- H04L1/0078—Avoidance of errors by organising the transmitted data in a format specifically designed to deal with errors, e.g. location
- H04L1/0083—Formatting with frames or packets; Protocol or part of protocol for error control
Landscapes
- Engineering & Computer Science (AREA)
- Computer Networks & Wireless Communication (AREA)
- Signal Processing (AREA)
- Computer And Data Communications (AREA)
- Communication Control (AREA)
Abstract
PURPOSE:To enable to perform the processing of control steps different in frame architecure by means of one circuit constitution, by switching the two control means at the change-over circuit with the instruction from the data processor and altering the processing mode. CONSTITUTION:In case of data reception of the high level data link control steps, the change-over circuit 10 inputs the first flag to the first data buffer DB4 and the specific data detection circuit 7'' in the state of solid lines as shown in Figure with the instruction of the data processor 2, and the cricuit 7'' detects it and closes the gate circuit 8. Succeedingly, the data are sequentially transferred to the second DB5 and the third DB9, but the circuit 8 is closed and the flag is not fed to the unit 2. After this, the circuit 8 is opened and the data are fed to the unit 2. When the final flag is input, the circuit 7'' detects this, the circuit 8 is closed, and the insepction of error in the data is made at the operation circuit 6 and the result is informed to the unit 2. In the case of the basic type data transmission and control steps, the circuit 10 is in the state of dotted lines in Figure, the data are fed to DB9, and the output of DB9 is fed to the unit 2 and the circuit 6, for error inspection.
Priority Applications (1)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
JP54060937A JPS5953743B2 (en) | 1979-05-17 | 1979-05-17 | Communication control device |
Applications Claiming Priority (1)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
JP54060937A JPS5953743B2 (en) | 1979-05-17 | 1979-05-17 | Communication control device |
Publications (2)
Publication Number | Publication Date |
---|---|
JPS55153453A true JPS55153453A (en) | 1980-11-29 |
JPS5953743B2 JPS5953743B2 (en) | 1984-12-26 |
Family
ID=13156782
Family Applications (1)
Application Number | Title | Priority Date | Filing Date |
---|---|---|---|
JP54060937A Expired JPS5953743B2 (en) | 1979-05-17 | 1979-05-17 | Communication control device |
Country Status (1)
Country | Link |
---|---|
JP (1) | JPS5953743B2 (en) |
Cited By (1)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
JPH02100749A (en) * | 1988-08-26 | 1990-04-12 | Tektronix Inc | Data-buffer |
-
1979
- 1979-05-17 JP JP54060937A patent/JPS5953743B2/en not_active Expired
Cited By (1)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
JPH02100749A (en) * | 1988-08-26 | 1990-04-12 | Tektronix Inc | Data-buffer |
Also Published As
Publication number | Publication date |
---|---|
JPS5953743B2 (en) | 1984-12-26 |
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