JPS62159256A - Memory data checking system - Google Patents

Abstract

PURPOSE:To detect completely an address where an error occurred by performing a parity check while a CPU is using the memory data and reporting the result of the parity check to the CPU in the next memory cycle. CONSTITUTION:A CPU 100 transmits a memory address 104 and a memory 101 transmits the memory data 105 corresponding to the address 104. Then the CPU 100 uses the data 105 after it is fixed and starts its processing. At the same time, a parity checker 103 performs the parity check of the data 105 and delivers the result of this parity check in the form of a parity signal 106. A latch circuit 200 latches the signal 106 by a latch pulse 203 and supplied it to the CPU 100 in the form of a parity signal 201. Then the CPU 100 checks the signal 201 in the next memory cycle. While an address register 205 latches the relevant address only when a parity error is detected and delivers it as an address 206 where a memory error occurred.

Description

DETAILED DESCRIPTION OF THE INVENTION [Field of Industrial Application] The present invention relates to a memory data checking method for a process control device using a high-speed memory.

[Conventional technology]

In the conventional method, as shown in FIG.
Outputs 05. The parity checker 103 checks the data and sends the result to the CP as a parity signal 106.
Send to U100. In this method, as shown in the time chart of FIG.

Since the parity signal 106 is established after a delay of 5 TD when the memory output data 105 is established, the CPU 100 waits for operation for this TD, which becomes a bottleneck in speeding up.

[Problem that the invention seeks to solve]

In the above-mentioned conventional technology, the waiting time TD may be longer than the delay time of the memory alone, and even if high-speed memory is used, the effect may not be obtained. The purpose of the present invention is to enable the CPU to operate within the operating time of the high-speed memory itself, and also to enable checking of memory output data in the same manner as before. [Means for solving the problem] The above-mentioned The objective is achieved by C performing a parity check while the CPU is using memory data and reporting the result to the CPU in the next memory cycle.

[Effect]

The parity check circuit checks the same data while the CPU is using memory output data, and reports the result to the CPU in the next memory cycle, so the operating time of the parity check circuit does not make the CPU wait. Also, you can definitely check the memory data.

〔Example〕

FIG. 1 shows an embodiment of the present invention. CL' U 100
sends out memory address 104, memory 101 sends out memory data 105 corresponding to that address, and CPL
Jloo is waiting for that data to be established.

Processing begins using that data. At the same time, the parity checker 103 performs a parity check on the data 105 and outputs the result as a parity signal 106. ePUl
The latch circuit 200 is activated by the latch pulse 203 from oo.
latches the parity signal 106 and inputs it to the CPU 100 as a latched parity signal 201. C.P.
U checks this signal in the next memory cycle,
Also.

The address register receives the parity signal 106. With the latch pulse 203, the pulse 210 that passes through the gate 202 latches the address only when a parity error occurs, and outputs it as the address 206 where the memory error occurred.

FIG. 4 is a timing chart of the above embodiment. @4
At the establishment point 301 of the memory output data 105 in the figure (,
'F'U100 enters operation. After the operating time TD of the checker 103, it is latched by the latch pulse 203 and held until the first cycle.

As an effect of this embodiment.

1.0 PU means that the memory operates at high speed.

2. The check result is definitely input to the CPU in the next cycle.

& The address that caused the parity error can be reliably identified.

〔Effect of the invention〕

According to the present invention, the CPU can effectively utilize the memory speed, and at the same time, the check can be performed reliably.

Furthermore, since the address where the error has occurred can be reliably grasped, it is possible to construct a high-speed, highly reliable control device.

[Brief explanation of drawings]

FIG. 1 is a block diagram showing one embodiment of the present invention. FIG. 2 is a block diagram showing the prior art, and FIGS. 3 and 4 are time charts showing the prior art and an embodiment of the present invention. 100...C1-'U, 101...Memory, 103
...Parity checker, 104...Memory address, 105...Memory output data.

Claims (1)

[Claims] 1. When performing a parity check on output data from the memory, the parity check is performed on the data at the same time as the data is sent out, the result is latched, and the parity check result of the previous cycle is sent out in the next memory cycle. A memory data check method that is characterized by: 2. A memory data check method according to claim 1, characterized in that address data at that time is latched only when a parity check error is detected.