JPS61206058A - Memory controller - Google Patents

Abstract

PURPOSE:To detect always destruction of holding data by executing a parity checking of memory data at the time of the scanning leading action in a memory fresh action by a direct memory access controller. CONSTITUTION:A DMA transfer for a memory access necessary to a memory fresh from the memory to an I/O by a direct memory access DMA controller 2 is obtained by inputting the output signal of a timer 1 to the controller 2. At such a case, a parity bit is generated by a parity bit generating circuit 4, the symbol '0' is outputted to a parity data signal line 108 at the timing of the memory leading and the symbol '1' is outputted to the line 108 only when the parity error is generated. Consequently, the data of the line 108 are transferred to a CK terminal of an FF 9 for detecting the parity error only by the timing of the memory leading. Thus, the parity error can be detected, namely, the destruction of the holding data can be always detected.

Description

DETAILED DESCRIPTION OF THE INVENTION Trap i and 1 The present invention relates to a memory control device, and more particularly to a random access memory control device that is used in a data processing device and requires a refresh operation.

Prior Art Conventionally, when detecting a parity error in data held in a memory device, a CPU (central processing f, i
The parity error detection circuit operates and performs a parity check only when the controller executes a memory read.

Such a parity error detection method has a drawback in that it is impossible to detect destruction of memory-held data unless the CPU executes memory access to the address where the data is destroyed.

SUMMARY OF THE INVENTION An object of the present invention is to perform a parity check on memory data during a scan read operation in a memory refresh operation without the need for the CPU to execute memory access to an address where data destruction has occurred. An object of the present invention is to provide a memory control device that can always detect destruction of retained data.

A memory control device according to the present invention includes means for generating execution timing of a memory refresh operation, memory access means for performing a memory scan read operation at each execution timing, and memory access means for performing a memory scan read operation at each execution timing. The configuration includes parity detection means for performing a parity check on read data.

1. Next, the present invention will be described in detail with reference to the drawings showing one embodiment of the present invention.

In the figure, an output signal line 101 of interval timer 1
is directly connected to the DMA request input terminal (DRQ) of the DMA (direct memory access) controller 2. The memory read/write control circuit 10 connects D via an address signal line 103 and a control signal line 102.
It is connected to the MA controller 2 and also to the bidirectional data bus buffer 3 via the buffer enable signal [1113, and further connected to the input of the AND gate 7 and the input of the AND gate 11 via the memory read signal line 109. and bidirectional data bus buffer 3. Furthermore, the control circuit 10 is connected to the data holding memory 6 and the parity data holding memory 5 via a memory access address signal line 111 and a memory control signal line 112, respectively.

The bidirectional data bus buffer 3 is connected to the data bus line 105.
The parity bit generation circuit 4 is connected to the data holding memory 6 and the buffer with Hiah-Z (high impedance) 8 via the data bus signal line 104.
connected to an external data bus.

The parity bit generation circuit 4 includes a parity data signal line 1
The output terminal of the AND gate 7 is connected to the output terminal of the AND gate 7 via a line 08, and to the input terminal of the parity data holding memory 5 and the AND gate 11 via a parity data write data signal line 106, respectively. The input terminal of AND gate 7 is
It is connected to the parity data holding memory 5 via a memory read data signal line 107. The output terminal of the AND gate 11 is connected to the clock of the parity error detection F/F (flip 70 tube) 9 via the error signal line 114.
connected to the terminal. The data holding memory 6 is connected to the buffer 8 with Hiah-2 via a read signal line 110.

Next, the operation of the above configuration will be explained in order.

DMA transfer for memory access necessary for memory refreshing from memory to l10 (input/output device) by DMA controller O-2 is performed by transmitting a constant square wave signal output from interval timer 1 via output signal line 101. It can be obtained by inputting it to the DMA request terminal of the DMA controller 2. Memory read by DMA transfer for memory refresh generated by DMA controller 2,
The address signal of the address signal line 111 and the memory control signal line 112 are used to read data from the held data memory 6 and the parity data holding memory 5 by the memory read/write control circuit 10 in the same way as the memory read by the CPU.
memory control signals are generated.

In the memory read access for memory refresh by the DMA controller 2, the data read from the retained data memory 6 is transferred to the buffer 8 with Hi ah-Z only at the timing of memory read by the memory read signal 109 via the read data signal [1110. The data is input to the parity bit generation circuit 4 via the data bus signal line 105 as input data for parity bit generation.

On the other hand, the data read from the parity bit holding memory 5 is input to the AND gate 7, but only when the memory read signal on the memory read signal line 109, which is the other input to the AND gate, indicates a memory read. The data on the memory read data signal line 107 is transmitted to the parity data signal line 108 and taken into the parity bit generation circuit 4, and the parity bit generation circuit 4 executes parity bit generation together with the data on the data bus signal line 105.

In this parity bit generation, since the parity bit is generated at the time of memory write, the parity data signal line 10B is set to "0" at the memory read timing.
is output and only if a parity error has occurred,
“1” is output to the parity data signal [1108.

Therefore, the data on the parity data signal line 108 is A
Memory read signal line 10 which is an input signal of ND gate 7
9, the parity error detection F/
It is transmitted to the C1ock terminal of F9. Then, parity bit signal line 1, which is a parity error when reading memory,
The change from O' of 06 to "1" is latched by the parity error detection F/F 9, and the state of occurrence of a parity error is maintained. As a result, parity errors can be detected not only in memory read by the CPU but also in DMA transfer memory read for memory refresh by the DMA controller 2.

11 Wataru 11 As explained above, according to the present invention, the presence or absence of a parity error in data check is detected at the memory refresh operation timing by scan read by the DMA controller. This has the effect of being able to inexpensively detect data corruption errors that exist on memory that has not been used.

[Brief explanation of drawings]

The figure is a block diagram of an embodiment of the invention. Explanation of symbols of main parts 1...Timer

Claims (1)

[Claims] A memory control device for a random access memory requiring a memory refresh operation, comprising: means for generating an execution timing for the memory refresh operation; a memory access means for performing a memory scan read operation at each execution timing; and the scan read operation. and parity detection means for performing parity check on memory read data at the timing of.