JPS6252649A - Hard error detector for memory element - Google Patents

Abstract

PURPOSE:To make a checking-only memory unnecessary and to simplify the constitution by writing and reading two types of data patterns with respect to all memory elements while the system is reset, comparing said patterns and detecting the hard error of the memory. CONSTITUTION:The titled detector operates only when the system at the time of turning on a system power source is reset. At this time, when a clock CL is transmitted to a control signal generator 12, first a '1' pattern data generator 14 operates, and writes data in a memory element to be inspected 11 through a three state buffer 19. Then a data comparator 16 compares the written data with data outputted from said memory 11, and a flip flop 17 latches them. This time, checking is conducted in the same manner through the use of a '0' pattern generator 15. When the memory is normal, an address generator 13 increments the address, and inspections '1' and '0' are conducted.

Description

[Detailed Description of the Invention] [Industrial Application Field] The present invention relates to a hard error detection device for memory elements that detects hard errors in memory elements mounted on memory boards in computer systems and the like. be.

[Conventional technology]

Figure 2 shows, for example, Intel's 1984 OEM System Handbook (OEM 5ystenHand).
1 is a block diagram showing a conventional hard error detection device for a memory element described in P. 6-1 to P. 6-2, in which 1 is a memory element for data storage as a memory element to be inspected, and 2 is a memory element for data storage as a memory element to be inspected. A parity bit storage memory element 3 stores a parity bit for parity checking, and 3 is a parity checker/generator, which uses a data bus 4 connected to the memory element 1 to be tested for data storage during memory writing. After generating a parity bit by referring to the flowing information, the parity information is written to the parity bit storage memory element 2 via the parity bit write line 5, and when reading the memory, the parity information is written to the parity bit storage memory element 2 and the data bus 4. The parity check is performed by referring to the information flowing to the parity bit continuation line 6 connected to the parity bit line 6 connected to the parity bit line 6. A flip-flop 7 stores the result of the parity check determined by the parity checker/generator 3.

Next, the operation will be explained. When writing data to the memory element under test 1, when the write data flowing through the data bus 4 becomes valid, the validity checker/generator 3 functions as a generator, and writes a pair of data to the contents of the data bus 4. The resulting parity bit is output to the parity bit write line 5. Then, at the same time as writing the data to the memory element 1, the parity bit is written to the memory element 2 for storing parity pinto.

Next, during a read operation of the memory element 1 to be tested, the memory element 1 to be tested and the memory element 2 for storing parity bits are simultaneously read, and the output thereof is supplied to the parity checker/generator 3 functioning as a parity checker. By doing so, it is determined whether or not a hard error has occurred in the memory element 1 to be tested based on the content of the output, and the result is stored in the flip-flop 7.

[Problem that the invention seeks to solve]

Since the conventional hard error detection device for memory elements is configured as described above, it always generates a parity bit and performs a parity check during memory write and read operations, so the memory cycle is reduced by that time. becomes slower. In addition, in addition to the memory element to be tested, a memory element dedicated to parity bits must be added, which has a large impact on the cost and mounting space of large-capacity memory boards equipped with a large number of elements. Furthermore, since it is a parity check, there are problems such as an error detection rate of less than 172 seconds.

This invention was made to solve the above-mentioned problems. It is possible to speed up the memory cycle, eliminate the need for a memory element dedicated to checking, and thereby construct an inexpensive and large-capacity memory board. It is an object of the present invention to provide a hard error detection device for a memory element, which is capable of detecting errors in all bits at the time of checking.

[Means for solving problems]

The hard error detection device for memory elements according to the present invention includes:
During system startup and system restart, the system itself is in a reset state; it operates and writes two types of data patterns "1" and "0" to all memory elements one after another. Through comparison, hard errors in the memory element are detected.

[For production]

The hard error detection device for memory devices according to the present invention does not require a memory device for parity bit checking, and can detect hard errors without affecting normal memory read cycles and memory write cycles. Therefore, faster memory cycles can be achieved.

Furthermore, as a side effect, all memory will necessarily be cleared when the system starts, and the conventional memory clearing process using software becomes unnecessary.

[Embodiments of the invention]

An embodiment of the present invention will be described below with reference to the drawings. 1st
In the figure, 11 is a memory element to be tested for data storage;
12 is a control 1 word generator consisting of a counter and a decoder; 13 is an address generator consisting of a counter; 14 is an "l" pattern data generator that outputs all 1m pattern data according to instructions from the control signal generator 12; 15 is a control All “0” due to instructions from signal generator 12
“0” pattern data generator that outputs pattern data, 16 is “1” pattern data generator 14
A data comparator 17 compares the data output from the "0" pattern data generator 15 and the data read from the memory element 11 to be tested, and 17 is the data comparator 16 in which a hard error in the memory element 11 to be tested is detected. and a flip-flop that latches it; 18 is a three-state buffer that drives the memory element 11 to be tested using memory read commands and memory write commands for the memory element 11 to be tested that are output from the control signal generator 12; 19 is a control signal generator a three-state buffer that drives the memory element 11 under test using an address signal for the memory element 11 outputted from the memory element 12;
20 indicates all '1' or all ' for the memory element 11 to be tested output from the address generator 20.
21 is a clock signal line that supplies a clock signal for operating this device to the control signal generator 12. Furthermore, the three-state buffer 18 .19.20 operates only when the system is in the reset state and is always in the three-state state when the system is operating.

In the hard error detection device for memory elements configured in this way, 1. The device operates only when the system itself is in a reset state, such as when the system power is turned on or when the system is restarted. First, when a clock signal line CL having a frequency equal to or slower than the response speed of the memory element under test is sent to the control signal generator 12 through the clock signal line 21, various control signals are generated in accordance with this clock signal. is generated and supplied to each part. First, the "1" pattern data generator 14 operates to output all "1" data, which is written into the memory element 11 to be tested through the three-state buffer 19. In the next cycle, read and “
The data output from the 1" pattern data generator 14 and the data output from the memory element under test 11 are compared in the data comparator 16, and the result is latched in the flip-flop 17 for storing errors. If an error occurs, the CPU (not shown) is instructed to immediately stop the operation.If no error is detected, the process proceeds to the next cycle, and this time, the same check as above is performed using the "0" pattern data generator 15. Then, when the write/read conveyor operations for both the "1" pattern and the "0" pattern are completed normally, the counter in the address generator 13 is counted by 1 at the next clock. , the address is incremented and the write/read conveyor operation of the "l" pattern and "0" pattern is performed again.In this way, the address generator 13 finishes counting the addresses of the target memory element 11 to be tested. When the count is counted up, the operation of this device is ended and the system waits for the system reset state to be released and system operation to start.Once the system reset state is released, the three-state buffers 1B, 19. 20
is fixed in a floating state. Further, when an error occurs, the flip-flop 17 turns on the LED to notify the occurrence of the error, and also issues an interrupt command to the system CPU to notify the occurrence of the error.

Note that although the above example shows the case where there is one memory element to be tested, this device originally exhibits its performance as the number of memory elements increases, so it is possible to use a plurality of memory elements to be tested. In this case, the output of the address generator 13 may be decoded.

Moreover, if such a circuit is integrated into an LSI and sealed in a single pancake, a hard error detection device for a memory element that is highly useful, inexpensive, and takes up a small space can be realized.

〔Effect of the invention〕

As described above, according to the present invention, when the system is in the reset state, hard errors are detected by writing and comparing two types of data patterns "1" and "0" to the memory element under test. Since it is a detection method, it is possible to perform inspection without affecting normal memory cycles, and accordingly, it is also possible to speed up memory cycles. Furthermore, since a memory element for hard error checking is not required, space and cost can be reduced. Furthermore, according to the present invention, all memory is necessarily cleared when the system is started, so that there is an effect that the memory clearing operation using software, which was conventionally required, is no longer necessary.

[Brief explanation of the drawing]

FIG. 1 is a block diagram showing a hard error detection device for a memory device according to an embodiment of the present invention, and FIG. 2 is a block diagram showing a conventional hard error detection device for a memory device. If is a memory element to be tested, 12 is a control signal generator, 13 is an address generator, and 14 is "1"
15 is a "0" pattern data generator, 16 is a data comparator, 17 is a flip-flop, 1B, 19.20 is a three-state buffer. Figure 1 18.19,20 Nissley Cheese Pa Nofa 2nd
Illustration procedure amendment (voluntary)

Claims (3)

[Claims] (1) A control signal generator that generates a control signal in response to a clock pulse, an address counter that increments an address according to instructions from the control signal generator, and outputs data in an all "1" pattern according to instructions from the control signal generator. “1” pattern data generator and all “0” according to instructions from the control signal generator.
A “0” pattern data generator outputs pattern data, and an output signal of the “1” pattern data generator and an output of the “0” pattern data generator are sent to the address specified position of the address counter according to instructions from the control signal generator and the “0” pattern data generator. A memory element to be tested into which a signal is written and read, a data comparator which detects a mismatch between the read output of the memory element to be tested and the output signal of the "1" pattern data generator or the "0" pattern data generator, and this data comparator. A hard error detection device for a memory element, comprising: a flip-flop circuit that stores a mismatch detection output of as an error signal. (2) The control signal generator writes a “1” or “0” pattern signal to the entire area of the memory element to be tested, reads it out and compares it to determine the error, and detects a hard error in the entire area of the memory element to be tested. If the pattern signal does not exist, a pattern signal different from the previous one is written in the entire area of the memory element to be tested, and then read out and compared to determine whether it is a hard error. Hard error detection device for memory device as described. (3) Hard error detection for a memory element according to claim 1, wherein writing and reading of the pattern signal to the memory element to be tested is performed when a system using the memory element to be tested is reset. Device.