JPH0535652A - Dma controller - Google Patents

Abstract

PURPOSE:To perform the comparing of the DMA data of a DMA source and a DMA destination and to perform the data transfer retrying at the time of the comparing error. CONSTITUTION:A DMA controller 1 is constituted of an address storing part 2, a data storing part 3, an address and data interface part 4, a data comparing part 5, a control register 6, an address counter 7 and a data buffer 8 for comparing, and when the data are compared by the data comparing part 5 and a comparing error occurs, a data comparing error signal 11 is sent to the address storing part 2 and a DMA control part and the storing of the address at the time of the error and the timing of a next DMA action are generated.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a DMA (Direct Memory Access) controller, and more particularly to a storage means capable of temporarily storing addresses and data contents, and D
D having compare means for comparing MA source data and DMA destination data and retry means for retrying DMA
Regarding the MA controller.

[0002]

2. Description of the Related Art Conventionally, in a DMA controller, a DMA
The source and DMA destination data are not compared and DM
A parity error or the like is detected for the first time in the first memory read after the A transfer.

[0003]

As described above, since the conventional DMA controller does not compare the data, the detection of the data error at the time of DMA must depend on the external circuit. In this case, if a parity check circuit or the like is used, a data error will not be detected until the first memory read after the DMA transfer.
There is a problem that it is difficult to perform MA retry.

In addition, in order to investigate the address at the time of data error, logging of PKG operation and the like must be stored, and the logging recording area must be assigned to the system or the storage device on the PKG. There was a problem.

An object of the present invention is to provide a DMA controller that can easily perform a DMA retry.

Another object of the present invention is to provide a DMA controller that does not need to be assigned a logging recording area in address investigation at the time of data error.

[0007]

A DMA controller according to the present invention comprises a first storage device for temporarily storing data to be transferred by DMA and a first storage device for temporarily storing an address when a DMA transfer failure occurs. It is characterized by including a second storage device and a retry means for performing a retry with the number of times set in the control register as the maximum number.

[0008]

EXAMPLES The present invention will be described below with reference to examples.

Referring to FIG. 1, DMA controller 1
Is composed of a 24-bit address storage unit 2, a 16-bit data storage unit 3, an address / data interface unit 4, a data compare unit 5, a control register 6, an address counter 7, and a compare data buffer 8. The address counter 7 is Address 24 on the internal address bus 9
Bits are sent to the address / data interface unit 4 and the address storage unit 2. The address / data interface unit 4 sends and receives an address and data to and from the memory, and at the same time, the internal data bus 10 allows the data storage unit 3 and the data storage unit 3, respectively.
Data compare buffer 8 and control register 6
Sending data to. The data compare section 5 compares the 16-bit data from the data storage section 3 with the 16-bit data from the compare data buffer 8,
When there is a compare error, the data compare error signal 11 is sent to the address storage unit 2 and the DMA control unit 1.
Send to 2. The transmitted signals are used as the timing for storing the address at the time of reading the data in which the error occurred and also as the timing for the next DMA operation.

FIG. 2 shows the configuration of a system using the DMA controller 1. Here, the DMA controller 1 reads the data from the MEMI 13 and outputs the MEMII 1
The operation of writing the data to 4 is performed.

FIGS. 3 and 4 show the timing of memory memory transfer. FIG. 3 shows normal timing, and FIG. 4 shows compare timing.

In FIGS. 3 and 4, CLK15 is the main D
It is a basic clock input to the MA controller, and normally one clock completes one DMA cycle. DAT
The A / ADDRESS 17 outputs the compare read address 21, the compare read data 22, the read address 23, the read data 24, the write address 25, and the write data 26, respectively, and the respective addresses are latched using ALE outside the DMA controller. . Also, A
The LE 16 is also output when the compare read address 21 is latched at the time of compare in addition to the normal cycle.

When the compare read is performed, the MRD 18 is divided into two outputs, one during the compare read and the other during the normal read, and at the timing of the compare read, the CMPRD 20 is output and the compare read is performed. Can be recognized.

FIG. 5 is a data transition diagram of a system using the DMA controller 1. In FIG. 5 (hereinafter referred to as 5-), the DMA controller 1 reads the data A from the MEMI 13, and the data of FIG. After storing the data in the storage unit 3, the data A is written to the MEMII 14 in 3-. After the data A ′ is read from the MEMI 13 at 5-, the data is written to the data compare section 5 through the compare data buffer 8 shown in FIG. Compare with.

The above 5 to 5 are normal compare D
The MA cycle.

Next, in 5-, the next data B is read from the MEMI 13, temporarily stored in the data storage section shown in FIG. 1, and then written in the MEMII 14 in 5-. In 5-, the same operation as in 5- is performed, but in this case a compare error occurs, so the data compare error signal 1 shown in FIG.
1 is sent, the address at the time of error is stored in the address storage unit 2, the data compare error signal 11 is sent to the DMA control unit 12, and the DMA control unit makes a retry.

5 to 5 are the retry processing 5-
Since the result of the comparison in step 5 was OK, the next C data is read in step 5-10. 5-10 to 5-15 once perform a retry process and an error occurs in the compare of 5-15, so the system is down in 5-16. At this time, the control register is set to retry processing once.

The above retry processing is performed the number of times specified in the control register 6 at the time of initialization when the data compare error signal 11 described above is input to the DMA control unit 12, and even if the final retry is performed. When an error occurs, the present DMA controller 1 stops its function after storing the address where the error occurred.

[0019]

As described above, according to the present invention, the storage means capable of temporarily storing the address and the content of the data is provided, and further the compare means for performing the data comparison of the DMA destination and the DMA source is provided. There is an effect that can be immediately retried.

[Brief description of drawings]

FIG. 1 is a block diagram showing a DMA controller according to the present invention.

FIG. 2 is a configuration diagram of a system using the DMA controller shown in FIG.

FIG. 3 is a timing diagram of the system shown in FIG.

4 is a timing diagram of the system shown in FIG.

FIG. 5 is a data transition diagram of a system using the present invention.

[Explanation of symbols]

1 DMA controller 2 Address storage section 3 data storage 4 Address / data interface section 5 Data compare section 6 Control register 7 address counter Data buffer for 8 compare 9 Internal address bus 10 Internal data bus 11 Data compare error signal 12 DMA control section 13 MEMI 14 MEMII 15 CLK 16 ALE 17 DATA / ADDRESS 18 MRD 19 MWR 20 CMPRD

Claims (3)

[Claims] 1. A DMA comprising memory memory transfer means.
The controller is provided with a storage unit for temporarily storing data transferred by DMA, and the data read from the memory by the DMA transfer and temporarily stored in the storage unit and the data are written in the memory by the DMA transfer. A DMA controller having a compare means for immediately comparing data read at the same address. 2. A DMA comprising memory memory transfer means.
The controller includes a first storage unit for temporarily storing data transferred by DMA, the data read from the memory by DMA transfer and temporarily stored in the first storage unit, and the data for DMA transfer. And a second storage means for temporarily storing the address of the data at the time of a compare error, and a compare means for comparing with the data read at the same address immediately thereafter. 2. A DMA controller having read means for reading the address from the second storage means to know the address of the data at the time of a compare error. 3. DMA with memory memory transfer means
The controller has a storage unit for temporarily storing data transferred by DMA, and the data read from the memory by DMA transfer and temporarily stored in the storage device and the data written in the memory by DMA transfer. Then, the DMA controller having a compare means for comparing the data read at the same address immediately after that and a retry means for maximizing a preset number at the time of a compare error.