JPH04103143A - Semiconductor integrated circuit - Google Patents
Semiconductor integrated circuitInfo
- Publication number
- JPH04103143A JPH04103143A JP2221577A JP22157790A JPH04103143A JP H04103143 A JPH04103143 A JP H04103143A JP 2221577 A JP2221577 A JP 2221577A JP 22157790 A JP22157790 A JP 22157790A JP H04103143 A JPH04103143 A JP H04103143A
- Authority
- JP
- Japan
- Prior art keywords
- output
- buffers
- outputs
- signal
- decoder
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Pending
Links
- 239000004065 semiconductor Substances 0.000 title claims abstract description 8
- 239000000872 buffer Substances 0.000 claims abstract description 25
- 238000010586 diagram Methods 0.000 description 2
- 230000000694 effects Effects 0.000 description 2
- 230000007257 malfunction Effects 0.000 description 2
- 230000002950 deficient Effects 0.000 description 1
Landscapes
- Testing Or Measuring Of Semiconductors Or The Like (AREA)
- Tests Of Electronic Circuits (AREA)
Abstract
Description
【発明の詳細な説明】
〔産業上の利用分野〕
本発明は半導体集積回路、特に多ビンの出力バッファを
有する半導体集積回路に関する。DETAILED DESCRIPTION OF THE INVENTION [Field of Industrial Application] The present invention relates to a semiconductor integrated circuit, and particularly to a semiconductor integrated circuit having a multi-bin output buffer.
従来、この種の半導体集積回路は出力バッファの駆動能
力については固定の駆動電流でしか使用出来ない回路構
成であった。Conventionally, this type of semiconductor integrated circuit has a circuit configuration that can only be used with a fixed drive current in terms of the drive capability of the output buffer.
上述した従来の半導体集積回路はLSIテスターによる
カスタムLSIの試験時において、複数の出力ビンが同
時に変化する試験パターンではノイズ等による誤動作が
発生し、良品が不良品となるケースが発生するという欠
点がある。The above-mentioned conventional semiconductor integrated circuit has the drawback that when testing a custom LSI using an LSI tester, a test pattern in which multiple output bins change simultaneously may cause malfunctions due to noise, etc., and a good product may become defective. be.
本発明の半導体集積回路は、出力電流を供給するトーテ
ムポール出力バッファと、3ステイト出力バッファと、
前記3ステイト出力バッファを制御する信号を出力する
デコーダとを含んで構成される。The semiconductor integrated circuit of the present invention includes a totem pole output buffer that supplies an output current, a 3-state output buffer,
and a decoder that outputs a signal for controlling the 3-state output buffer.
次に本発明について区画を参照して説明する。 The invention will now be described with reference to compartments.
第1図は本発明の一実施例を示すブロック図である。FIG. 1 is a block diagram showing one embodiment of the present invention.
第1図において、1はI 。L= n X−mA、
I as= m X −m Aの駆動能力を有し、出力
制御信号を人力とする出力バッファである。2〜4は出
力制御信号を入力とし、その出力が各々ワイヤードオワ
接続される3ステイトの出力バッファであり、バッファ
1の出力部に接続される。又I OL= n Xという
効果がある。In FIG. 1, 1 is I. L=nX-mA,
This is an output buffer that has a driving capability of I as = m X - m A and uses human power as an output control signal. Reference numerals 2 to 4 designate three-state output buffers which receive an output control signal and whose outputs are connected in a wired-or-off manner, and are connected to the output section of the buffer 1. There is also the effect that IOL=nX.
ている。5は出力バッファ2〜4に対するEnable
信号を出力するためのデコーダーである。ing. 5 is Enable for output buffers 2 to 4
This is a decoder for outputting signals.
デコーダー5の出力信号0LJTI〜3が“L”の場合
、出力バッファ2〜4の出力はハイインピーダンス状態
となる。又、“H“の場合、出力バッファ2〜4の出力
は出力制御信号と同極性の信号となり、出力信号AはI
OL= n X X 4 = n 、A1 oH=
m X X 4 = m waAの駆動能力を有す
る。When the output signals 0LJTI-3 of the decoder 5 are "L", the outputs of the output buffers 2-4 are in a high impedance state. In addition, in the case of "H", the outputs of output buffers 2 to 4 become signals with the same polarity as the output control signal, and output signal A becomes I
OL= n X X 4 = n, A1 oH=
It has a driving capacity of m X X 4 = m waA.
従って、デコーダー5の出力により、出力バッファの駆
動能力を制御することが可能である。Therefore, the output of the decoder 5 can control the driving ability of the output buffer.
以上説明したように、本発明は出力バッファの駆動能力
を可変に出来、LSIテスター使用時において複数ピン
の出力信号が同時に変化する試験パターンでもノイズ等
により誤動作を防止出来るAs explained above, the present invention makes it possible to vary the drive capacity of the output buffer, and when using an LSI tester, it is possible to prevent malfunctions due to noise etc. even in a test pattern in which the output signals of multiple pins change simultaneously.
第1図は本発明の一実施例を示すブロック図である。 FIG. 1 is a block diagram showing one embodiment of the present invention.
Claims (1)
ステイト出力バッファと、前記3ステイト出力バッファ
を制御する信号を出力するデコーダとを含むことを特徴
とする半導体集積回路。a totem pole output buffer that supplies the output current;
A semiconductor integrated circuit comprising: a state output buffer; and a decoder that outputs a signal for controlling the three-state output buffer.
Priority Applications (1)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
JP2221577A JPH04103143A (en) | 1990-08-23 | 1990-08-23 | Semiconductor integrated circuit |
Applications Claiming Priority (1)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
JP2221577A JPH04103143A (en) | 1990-08-23 | 1990-08-23 | Semiconductor integrated circuit |
Publications (1)
Publication Number | Publication Date |
---|---|
JPH04103143A true JPH04103143A (en) | 1992-04-06 |
Family
ID=16768923
Family Applications (1)
Application Number | Title | Priority Date | Filing Date |
---|---|---|---|
JP2221577A Pending JPH04103143A (en) | 1990-08-23 | 1990-08-23 | Semiconductor integrated circuit |
Country Status (1)
Country | Link |
---|---|
JP (1) | JPH04103143A (en) |
Cited By (2)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
JPH05304193A (en) * | 1992-04-28 | 1993-11-16 | Toshiba Corp | Semiconductor integrated circuit device and testing method of electrical characterstic thereof |
US5783963A (en) * | 1996-02-29 | 1998-07-21 | Lexmark International, Inc. | ASIC with selectable output drivers |
-
1990
- 1990-08-23 JP JP2221577A patent/JPH04103143A/en active Pending
Cited By (3)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
JPH05304193A (en) * | 1992-04-28 | 1993-11-16 | Toshiba Corp | Semiconductor integrated circuit device and testing method of electrical characterstic thereof |
US5783963A (en) * | 1996-02-29 | 1998-07-21 | Lexmark International, Inc. | ASIC with selectable output drivers |
KR100556045B1 (en) * | 1996-02-29 | 2006-05-17 | 렉스마크 인터내셔널, 인코포레이티드 | Custom semiconductors and their manufacturing methods, and devices controlled by data processors and custom semiconductors |
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