JPH0454522Y2 - - Google Patents

Description

[Detailed description of the invention] [Industrial application field] The present invention relates to a memory access circuit, and particularly to a memory access circuit in which each of a plurality of arithmetic processing units (hereinafter referred to as MPU) accesses the same memory. .

[Prior art]

As the functions of high-speed facsimile devices become more sophisticated, two MPUs are operated in parallel to perform various controls, and each MPU accesses the same memory to read and write data.

FIG. 2 is a block diagram of a memory access circuit shown in Japanese Patent Application Laid-Open No. 59-53958. MPU1
Address signals for MPU1 and MPU2 are applied to bus selector 4 via address control buses AB1 and AB2, and address signals for MPU1 and MPU2 are applied to decoder 6 and decoder 7, respectively. The output signal of the bus selector 4 is given to the memory 3. PMU1 and MPU2 are data buses
Data signals are given to the memory 3 via the bus selector 5 by DB1 and DB2, and data signals are obtained from the memory 3.

Bus selector 4 and bus selector 5 are the main
Decoder 6 to which the address signal of MPU1 is input
address bus AB1 or AB2 and data bus DB1 or DB by chip select signal CS1.
MPU1
When outputs an address signal, the memory is accessed via address control bus AB1 and data bus DB1. In other words, MPU1 operates preferentially. Chip select signal of decoder 6
Chip select signal CS2 of the decoder 7 which is outputted by the address signals of CS1 and MPU2
are input to AND gates 8, and the output signals of AND gates 8 are input to the set terminal ST of flip-flop 9, which serves as an access overlap detection circuit.
is given to. Furthermore, the MPU 2 provides an output signal R of "1" to the reset terminal RS of the flip-flop 9 at the time of access. The set output S output from the output terminal Q of the flip-flop 9 is
It is given to MPU2.

3 and 4 are flowcharts showing operations related to access by MPU1 and MPU2 in FIG. 2.

FIG. 3 shows the access operation of the MPU 1, and the main MPU 1 performs the access operation with priority over the access of the MPU 2, as described above. On the other hand, Figure 4 shows the access operation of MPU2,
The slave MPU 2 determines whether the set output S of the flip-flop 9 is "1" or "0". When the set output S is ``1'', the output signal R of the MPU 2 is set to ``1'' and is applied to the reset terminal RS of the flip-flop 9, and after the set output S is set to ``0'', the memory circuit 3 is reset at the same address. Perform the action to access.

[Problem that the invention attempts to solve]

As mentioned above, when accessing memory in the conventional memory access circuit, the secondary MPU 2 repeatedly judges whether or not the primary MPU 1 is in an access state, which places a large burden on the secondary MPU 2. , 2 and the memory 3, the high-speed control of the entire device is impaired.

In view of the above-mentioned problems, this invention reduces the burden on one MPU when accessing memory.
An object of the present invention is to provide a memory access circuit that can control the entire memory device at high speed.

[Means for Solving the Problems] The memory access circuit according to the present invention is configured such that a plurality of arithmetic processing units access the same memory. A decoder that separately provides control signals output by the processing device, a code converter that separately provides each decoder output via a gate when the control signal is input, and an output and identification code converter. a timing generation circuit which receives gate outputs connected to the arithmetic processing units as input, performs bus selection control between each arithmetic processing unit and the memory, and issues a standby control signal whose content changes at a timing related to this selection control; , comprising a logic circuit which receives the standby control signal and each of the decoder outputs that provide the control signals outputted by each arithmetic processing unit as inputs, and provides the output thereof to a standby state control terminal of each arithmetic processing unit. , the output of the code converter is used as an opening/closing control signal for the gate, and when any arithmetic processing unit is accessing the memory, the gate related to the other arithmetic processing unit is closed, and the timing generation circuit: When the other arithmetic processing device issues the control signal, the logic circuit issues a signal to put the arithmetic processing device into a standby state, and a plurality of arithmetic processing devices including the specific arithmetic processing device The present invention is characterized in that when the control signals are output simultaneously, priority is given to access by the specific arithmetic processing unit.

[Effect]

When one of the arithmetic processing units issues a control signal to access the memory, the code converter output closes the gates of the other arithmetic processing units, and the timing generation circuit is connected to the arithmetic processing unit that issued the control signal. Control selection. This ensures priority for the arithmetic processing device that accessed first.

During this time, when the other arithmetic processing unit issues a control signal for memory access, it is put into a standby state by the output of the logic circuit. When the access is completed, this waiting state is released, and the other arithmetic processing unit is accessed. When there is simultaneous access from a plurality of arithmetic processing units, the decoder output of the specific arithmetic processing unit is given to a timing generation circuit, and in response to this, the bus is selected preferentially for this specific arithmetic processing unit. .

[Embodiments] The present invention will be described in detail below with reference to drawings showing embodiments thereof.

FIG. 1 is a block diagram of a memory access circuit according to the present invention. 1st, 2nd MPU1, MPU
2 are connected to the memory 3 by address control buses AB1, AB2 and data buses DB1, DB2, so that the MPU1, MPU2 can access the memory 3. data bus DB
1, DB2, address buses AB1, AB2, chip select signals CS1, CS2 for memory, read signals RD1, RD2, write signals WR1, WR2
is now output. Chip select signal CS1, read signal RD1 and write signal WR1 of MPU 1 are applied to decoder 10.
MPU2 chip select signal CS2, read signal
RD2 and write signal WR2 are provided to the decoder 14. The MPUs 1 and 2 use address control buses AB1 and AB2 to send address signals to the memory 3 via the bus selector 4, and data signals are sent to the data buses DB1 and DB2.
DB2 connects memory 3 via bus selector 5.
It is designed so that it can be mutually given between MPU1 and MPU2. The MPU 1 generates a clock signal φ and applies the clock signal φ to the clock terminals CK of latch circuits 11 and 13 consisting of D flip clocks.
An inverted clock signal is applied to the timing generation circuit 18 via an inverter 201. When the input chip select signal CS1 and read signal RD1 are both "1", or when the chip select signal CS1 and write signal WR1 are input, the decoder 10
When both are "1", a signal of "1" is output. This signal is applied to the input terminal D of the latch circuit 11 and one side input terminal of the NAND gate 17 via the gate 20. The latch circuit 11 latches the signal from the gate 20 when the clock signal φ is applied, and converts the latch signal Q from 2 bits to 4 bits. One input terminal A of the code converter 12 and a timing generation circuit It is now being given to 18 people. When the input chip select signal CS2 and read signal RD2 are both "1", or when the chip select signal CS2 and write signal WR2 are both "1", the decoder 14
If so, a signal of "1" is output. This signal is applied to the input terminal D of the latch circuit 13 and one side input terminal of the NAND gate 19 via the gate 21. The latch circuit 13 latches the signal from the gate 20 when the clock signal φ is applied, and the latch signal is applied to the other input terminal B of the code converter 12. The code converter 12 uses, for example, an IC (74139) manufactured by Fujitsu Ltd., and when the signals a and b given from the latch circuits 11 and 13 are (a, b) = (0, 0), ( ₃ , ₂ , ₁ ,
Y ₀ ) = (1, 1, 1, 0) When (a, b) = (1, 0) ( ₃ , ₂ , ₁ ,
Y ₀ ) = (1, 1, 0, 1) When (a, b) = (0, 1) ( ₃ , ₂ , ₁ ,
Y ₀ ) = (1, 0, 1, 1) When (a, b) = (1, 1) ( ₃ , ₂ . ₁ ,
A signal is output as Y ₀ )=(0,1,1,1). This code converter 12
The Y ₁ and ₃ outputs are given to both input terminals of an AND gate 15, and the output signal d of the AND gate 15 is given to the gate 21 as its opening/closing signal. Further, _one output is given to one input terminal of the AND gate 16.

And the output signal d of the AND gate 15 is "1"
When the signal is "0", the gate 21 is opened and the output signal of the decoder 14 is applied to the latch circuit 13, and when the signal is "0", the output signal is cut off. In addition, the ₁ and ₂ outputs of the code converter 12 are connected to the AND gate 16.
The _two outputs are given to the gate 20 as opening/closing signals. The output signal of the AND gate 16 is applied to the timing generation circuit 18. and gate 20
When the output signal c whose output is " ₁ " is applied to the gate 20, the gate 20 is opened and the output signal of the decoder 10 is applied to the latch circuit 11, and when the output signal is "0", the output signal is cut off. do.

The input signal a of the timing generation circuit 18 is "0".
Then, the MPU2 address control bus
Bus selectors 4 and 5 are controlled to select AB2 and data bus DB2, and when input signal a is "1", bus selectors 4 and 5 are controlled to select address control bus AB1 and data bus DB1. It's summery. In addition, the standby signals ACK1 and ACK2 dataed by the timing generation circuit 18 are
is always "1", but when the control signals to the bus selectors 4 and 5 are removed, that is, when the memory access is completed, it is inverted from "1" to "0" by one clock of the clock signal φ. It's becoming like that.

The NAND gate 17 becomes "1" when the output signal of the decoder 10 or the standby signal ACK1 becomes "0".
The ready signal e is applied to the standby signal input terminal of the MPU 1. On the other hand, NAND gate 1
9 is the output signal of the decoder 14 or the standby signal ACK
When 2 becomes "0", the ready signal f of "1" is sent.
It is designed to be applied to the standby signal input terminal of MPU2. Both MPUs 1 and 2 can execute arithmetic processing when the ready signal is "1", but are in a standby state when it is "0".

Next, the operation of the memory access circuit configured as described above will be explained. Now, when MPU1 reads data from memory 3, chip select signal CS1
and sets the read signal RD1 to "1" while outputting an address signal. As a result, the output of the decoder 10 becomes "1", and the output signal a of the latch circuit 11 becomes "1" at the rising edge of the clock signal φ. This output signal of "1" is applied to input terminal A of code converter 12 and timing generation circuit 18.
Since a=1, the timing generation circuit 18 controls the bus selectors 4 and 5 to select the address control bus AB1 and the data bus DB1 to access the memory 3.

On the other hand, the ready signal e output by the NAND gate 17 becomes "0", and the MPU 1 enters an access standby state. Assuming that MPU2 is not accessing, signal b is "0", so ₂ ,
The _Y1 outputs are "1" and "0", and the output of the AND gate 16 is "0". At the same time, _three outputs "1" and "0" are given to the AND gate 15, and the output signal d
becomes "0" and the gate 21 is closed. During this time,
When the MPU2 accesses, the output signal of the decoder 14 becomes "1", and along with that signal, the standby signal ACK2 of the timing generation circuit 18 is given to the NAND gate 19, and the output of the NAND gate 19 becomes "0", and the MPU2 is in a standby state. become. gate 2
1 is closed, so the output of the decoder 13 does not change. When the above-mentioned MPU1 access ends, the timing generation circuit 18 sets the standby signal ACK1 to "0" at the end of the memory access.
to be reversed. Therefore, the ready signal e becomes "1" and the MPU 1 is released from the standby state. As a result, the MPU1 sets the chip select signal CS1 and read signal RD1 to "0". Then a=“0”
Then, the AND gate 15 output d becomes "0" and the gate 21 opens. As mentioned above, if the MPU 2 has accessed and is in the standby state, the output b of the latch circuit 13 becomes "1", the output of the code converter 12 becomes "0", and the gate 20 is closed. At this time, since the signal a is "0", the timing generation circuit 18 controls the bus selectors 4 and 5 to cause the MPU 2 to access the memory 3,
After that, set ACK2 to "0" and ready signal f=
Set it to "1" to release the MPU2 from the standby state.

As described above, on the contrary, when MPU2 accesses first, the same operation is performed, and the access of MPU2 is given priority.

When MPU1 and MPU2 access memory 3 at the same time, the output signals of decoders 10 and 14 are both "1", and latch circuits 11 and 13
The respective output signals a and b are both "1". Therefore, the _three outputs of the code converter 12 are "0" and the _two outputs are "1" and "0", and the output signal d of the AND gate 15 becomes "0", and the gate 21 is closed. on the other hand
The output signal of the AND gate 16 becomes "1", and the timing generation circuit 18 controls the bus selectors 4 and 5 to select the address control bus AB1 and the data bus DB1. In other words, in the case of simultaneous access, access by MPU 1 has priority. In addition, depending on the standby signals ACK1 and ACK2
The standby and standby cancellation operations of the MPUs 1 and 2 are the same as those already described.

Note that the present invention can be similarly applied to cases where three or more MPUs access one memory.

〔effect〕

As detailed above, according to the present invention, priority is given to the access of the MPU that is accessing first, and when multiple MPUs access the same memory circuit at the same time, priority is given to the access of a specific MPU.
While the MPU is being accessed, the MPU is placed in a standby state, and once the standby state is released, access can be started freely.
The MPU does not need to repeatedly judge whether or not it is being accessed.

Therefore, the memory access circuit of the present invention is an excellent memory access circuit that performs delayed access or reduces the burden on subordinate MPUs, and can access the memory immediately after other MPUs have finished accessing it, thereby achieving faster speeds. be effective.

[Brief explanation of the drawing]

FIG. 1 is a block diagram of a memory access circuit according to the present invention, FIG. 2 is a block diagram of a conventional memory access circuit, and FIGS. 3 and 4 are flowcharts showing access contents. 1, 2...MPU (processing unit), 3...Memory, 4, 5...Bus selector, 10...Decoder, 11...Latch circuit, 12...Code converter, 13...Latch circuit, 14 ...Decoder, 1
8... Timing generation circuit, AB1, AB2...
Address control bus, DB1, DB2...
data bus.

Claims (1)

[Claims for Utility Model Registration] In a memory access circuit configured to allow a plurality of arithmetic processing units to access the same memory, a control signal output by each of the arithmetic processing units to access the memory is specially provided. A decoder, a code converter that separately provides each decoder output via a gate when this control signal is input, and the output of this code converter and the gate output connected to a specific arithmetic processing unit as inputs. ,
A timing generation circuit that performs bus selection control between each arithmetic processing unit and memory and generates a standby control signal whose content changes at a timing related to this selection control, and outputs the standby control signal and each arithmetic processing unit. a logic circuit that receives each of the decoder outputs that provide the control signal to be input, and provides the output to a standby state control terminal of each arithmetic processing unit; The control signal is used as a control signal, and when one of the arithmetic processing units is accessing the memory, the gate related to the other arithmetic processing unit is closed, and the timing generation circuit causes the other arithmetic processing unit to generate the control signal. In this case, the logic circuit issues a signal to put the arithmetic processing device into a standby state, and when a plurality of arithmetic processing devices including the specific arithmetic processing device simultaneously output the control signal, A memory access circuit characterized in that the memory access circuit is configured to give priority to access by the specific arithmetic processing unit.