JPH07121429A - Dual port memory circuit - Google Patents

Abstract

PURPOSE:To provide a dual port memory circuit suitable for inter-processor communication dealing with massive data by using a random access memory and giving priority over one access as against memory access signals from two CPU by means of a mediation circuit. CONSTITUTION:A data bus connected to the data terminal DATA of SRAM 1 is connected to the data bus of a first port-side through a data bus input circuit 4 and an output circuit 5, and is connected to the data bus of a second port-side through an input circuit 6 and an output circuit 7. Address bus input circuits 2 and 3 and data bus input circuits 4 add 6 are constituted by three states buffers. The buses are connection-controlled by an access control signal inputted to an output enable terminal OE, and the access control signal is generated by the mediation circuit. The data bus output circuits 5 and 7 are constituted by the latch circuits of eight bits, and eight-bit data of SRAM 1 is fetched by a strobe signal which the mediation circuit generates.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a dual port memory circuit, and more particularly to a dual port memory circuit suitable for use in interprocessor communication handling a large amount of data.

[0002]

2. Description of the Related Art A dual-port memory circuit is used as a shared buffer for two CPUs in interprocessor communication because it can arbitrarily access and write and read from two directions.

Heretofore, a dual-port memory, which is a semiconductor device, has heretofore been available.
Since it has a maximum capacity of 8 Kbytes, a plurality of dual port memories are used for interprocessor communication handling a large amount of data.

[0004]

Although the price of a commercially available dual-port memory is several times as high as that of a random access memory, if the number of used dual-port memories is small, the problem is small. However, for example, when configuring a 128-Kbyte dual-port memory circuit, 16 commercially available dual-port memories are used, and there is a problem that such a large number of uses makes it very expensive.

The present invention has been made in view of such conventional problems, and an object thereof is to provide a dual port memory circuit which can be easily expanded to an arbitrary capacity at low cost.

[0006]

In order to achieve the above object, the dual port memory circuit of the present invention has the following configuration. That is, the dual port memory circuit of the present invention includes a random access memory; a first port side address bus for controlling connection between the address bus of the random access memory, the first port side address bus and the second port side address bus, respectively. An input circuit and a second port side address bus input circuit; a first port side data bus input / output circuit for respectively controlling connection between the data bus of the random access memory and the first port side data bus and the second port side data bus And a second port side data bus input / output circuit; a first port side CPU and a second port side CP
In response to the memory access signal of U, one of the address bus input circuit and the data bus input / output circuit on the side of the first port and the address bus input circuit and the data bus input / output circuit on the side of the second port is operated with priority. An arbitration circuit for
It is characterized by having.

[0007]

Next, the operation of the dual port memory circuit of the present invention constructed as described above will be described. Cheaply available,
In addition, a random access memory, which has a large capacity and is easily available, is used, and the arbitration circuit gives priority to one of the accesses to the memory access signals from the two CPUs.

Thus, according to the present invention, it is possible to provide a dual port memory circuit suitable for interprocessor communication handling a large amount of data, because it can be inexpensively and easily expanded to an arbitrary capacity.

[0009]

Embodiments of the present invention will be described below with reference to the drawings. 1 and 2 show a dual port memory circuit according to an embodiment of the present invention. In FIG. 1, 1 is a static random access memory (SRAM) which is a random access memory (RAM), and this SRAM 1 is a shared buffer of two microprocessors (CPU). In FIG. 1, one microprocessor (CPU
The side 1) is the first port side (left side in the figure), and the other microprocessor (CPU2) side is the second port side (right side in the figure), which is shown. In the present embodiment, the SRAM 1 is 128 Kbytes, for example.
Therefore, the data is 8 bits, but the address is 17 bits.

Address bus and chip select terminal (CS) connected to the address terminal (ADR) of SRAM 1
Is connected to the address bus on the first port side and the memory chip select signal line (P1CMCS-) via the address bus input circuit 2 on the side of the first port, and the address bus on the side of the second port. It is connected to the address bus on the second port side and the memory chip select signal line (P2CMCS-) via the input circuit 3. It should be noted that the fact that the signal name has a- (minus) at the end indicates that it has a meaning when it is "0", that is, it is low active. The same applies hereinafter.

The data bus connected to the data terminal (DATA) of the SRAM 1 is connected to the data bus on the first port side via the data bus input circuit 4 and the data bus output circuit 5, and is connected to the data bus input circuit 6 and the data bus. It is connected to the data bus on the second port side via the bus output circuit 7.

The address bus input circuits (2, 3) and the data bus input circuits (4, 6) are both three-state buffers, and access control signals (P1ACES-, P2ACES-) input to the output enable terminal (OE). )
The connection control of the bus is carried out by this, and this access control signal (P1ACES-, P2ACES-) is generated by the arbitration circuit (FIG. 2).

The data bus output circuits (5, 7) are composed of 8-bit latch circuits, and strobe signals (P1RWSTB-, P2RWSTB) generated by the arbitration circuit (FIG. 2).
The 8-bit data of SRAM 1 is fetched by (-). The output to the data bus on the corresponding port side is the gate (8,
9), the memory chip select signal (P1CMCS)
-, P2CMCS-) and memory read signal (P1MRD)
-, P2MRD-) are both performed when the low active condition is satisfied.

Output enable terminal (OE) of SRAM 1
The output of either the gate 11 or the gate 12 is applied as a control signal to the gate 1 through the gate 10.
1 (12) is a memory read signal P1MRD- (P2MRD-) from the CPU 1 (2) and an access control signal P1ACES- (P2ACES-) from the arbitration circuit (FIG. 2).
Emits an output when both are low active.

In short, the SRAM 1 has the access control signal P1ACES- (P2AC) from the arbitration circuit (FIG. 2).
The output enable operation state is set by the memory read signal P1MRD- (P2MRD-) of the CPU1 (2) within the period of ES-).

The write enable terminal (W
E) includes gate 14 and gate 15 through gate 13.
One of the outputs is applied as a control signal, but the gate 14 (15) causes the memory write signal P1MWR- (P2MWR-) from the CPU 1 (2) and the strobe signal P1RWSTB- from the arbitration circuit (FIG. 2). (P2RW
Outputs when both STB-) are active low.

In short, the SRAM1 has the strobe signal P1RWSTB- (P2RW) from the arbitration circuit (FIG. 2).
During the period of STB-), the CPU 1 (2) memory write signal P1MWR- (P2MWR-) enables the write enable operation state.

Next, the arbitration circuit will be described. In FIG. 2, the upper stage is the control circuit on the side of the first port (CPU1), and the lower stage is the control circuit on the side of the second port (CPU2), each of which has four flip-flops (F / F1 to 4) (F / F1). F5 to 8) and the three flip-flops (F / F2 to 4) (F / F6 to 8) operate with the same clock CK.
1 causes the lower control circuits (F / F6 to 8) to operate at a timing delayed by half a clock from the upper control circuits (F / F2 to 4), and when the CPUs 1 and 2 simultaneously access However, it is possible to perform competitive control without any trouble.

The memory chip select signal P1CMCS- (P2CMCS-) from the CPU 1 (2) is inverted by the inverter 22 (23) and applied to the D terminal of the F / F 1 (5). Further, the memory read signal P1MRD- (P2MRD-) and the memory write signal P1 from the CPU1 (2)
One of the MWR- (P2MWR-) is the gate 24.
It is applied to the clock terminal CK of F / F1 (5) via (25).

In short, the F / F 1 (5) is driven by the inverter 22 (2) at the timing when the memory read signal P1MRD- (P2MRD-) or the memory write signal P1MWR- (P2MWR-) falls from "1" to "0".
The output “1” of 3) is taken in and the positive phase output Q + is set to “1”.

The gate 26 has the positive phase outputs Q + and F of F / F1.
When the opposite-phase outputs Q- of / F6 are both "1", the output to the D terminal of F / F2 is set to "1". F / F6 negative phase output Q
The signal in the period in which-is "0" is the access control signal P2ACES- on the second port side described above.

The gate 27 has the positive phase outputs Q + and F of F / F5.
When the opposite-phase outputs Q- of / F2 are both "1", the output to the D terminal of F / F6 is set to "1". Reverse phase output Q of F / F2
The signal in the period in which-is "0" is the access control signal P1ACES- on the first port side described above.

The positive phase output Q + of F / F2 (6) is F / F3
The positive phase output Q + of the F / F 3 (7) applied to the D terminal of (7) becomes one input of the gate 28 (29) and the gate 30 (31).

The gate 28 (29) uses the positive phase output Q + of the F / F 4 (8) as the other input, and outputs either one of the both inputs to the D terminal of the F / F 4 (8). The signal during the period when the positive phase output Q + of the F / F 4 (8) is “1” is the CPU 1
The ready signal P1RDY + (P2RDY +) to (2) is obtained.

The gate 30 (31) is in the above-described gate 14 (15) during the period in which both the positive phase output Q + of the F / F 3 (7) and the negative phase output Q- of the F / F 4 (8) are "1". And a low-active strobe signal P1RWSTB- (P2RWSTB-) to the data bus output circuit 5 (7).

The gate 32 (33) is connected to the CPU 1
One of the reset signal RES- from (2) and the opposite phase output Q-("0") of the F / F3 (7) is used as a clear signal for F /
Output to the clear terminal CLR of F1 (5).

Further, the gate 34 (35) outputs a clear signal from F / F2 to 4 (F / F) when the output of the inverter 22 (23) and the output of the gate 24 (25) are other than "1".
6 to 8) Output to the clear terminal CLR.

The specific competition control operation will be described below with reference to FIG. F / F1 and 5 are cleared by the reset signal RES- from the CPU, and the positive phase output Q + is "0".
I have to. In addition, F / F2 to 4 are P1CMCS-
Before and P1MRD- / P1MWR- become low active, they are cleared by the output of the gate 34, and the positive phase output Q + is set to "0". Similarly, F / F6 to 8 are
Before P2CMCS- and P2MRD- / P2MWR- become low active, they are cleared by the output of the gate 35, and the positive phase output Q + is set to "0".

P1CMCS- becomes low active,
When P1MRD- / P1MWR- becomes low active, F / F1 sets the positive phase output Q + to "1". Similarly P
2CMCS- becomes low active and P2MRD- /
When P2MWR- becomes low active, F / F5 sets the positive phase output Q + to "1".

In FIG. 3, the CPU 1 accesses first and F /
After F1 sets the positive phase output Q + to "1" and F / F2 sets the normal phase output Q + to "1", the CPU2 accesses the F / F
5 shows the case where the positive phase output Q + is set to "1".
Since 2 and 6 operate at a timing shifted by a half clock, even if the F / F1 and 5 both set the positive phase output Q + to "1" at the same time, the gates 26 and 27 always act as F / F2. It is prohibited that either one of the same 6 first sets the positive phase output Q + to "1" and the other one sets the normal phase output Q + to "1".

When the F / F1 sets the positive phase output Q + to "1", the F / F2 sets the positive phase output Q + to "1" (P1ACES +) at the leading edge of the clock CK immediately after that, and the negative phase output Q +.
The P1ACES- of "0" is output from-.

As a result, the address bus input circuit 2 connects the address bus on the first port side and the chip select signal line, and the data bus input circuit 4 connects the data bus on the first port side. On the other hand, the data bus output circuit 5 is enabled by the gate 8 only when the memory read signal P1MRD- is input.

When the F / F2 sets the positive phase output Q + to "1", the F / F3 sets the normal phase output Q + to "1" and the negative phase output Q- to "0" at the next leading edge of the clock CK. So F
/ F1 is cleared. Since the D terminal input of the F / F2 is "0", the normal phase output Q + is "0" at the leading edge of the next clock CK when the F / F3 sets the normal phase output Q + to "1".
Then, the reverse phase output is set to "1".

As a result, the bus connection on the first port side is released, but the strobe signal P output from the gate 30 is output.
1RWSTB is "1" (P1RWSTB +) until F / F3 sets the positive phase output Q + to "1" after the F / F2 sets the positive phase output Q + to "1", and the F / F3 outputs the positive phase output Q.
It is "0" (P1RWSTB-) until the F / F2 sets the positive phase output Q + to "0" after the + is set to "1".

F / F2 sets the positive phase output Q + to "0" At the leading edge of the same clock CK, the F / F4 sets the normal phase output Q + to "1" and the negative phase output Q- to "0". . When the F / F4 sets the positive phase output Q + to "1", the ready signal P is sent to the CPU1.
1RDY + is provided. After confirming this, the CPU1 P
Since 1MRD- / P1MWR- is set to "1", F / F3 and 4 are cleared at that timing. Also, C
PU1 sets P1CMCS- to "1". This allows
The access from the CPU 1 ends.

In summary, the first port side can access the SRAM1 within the period of the access control signal P1ACES-. Specifically, in the write mode, the gate 14 causes the SRAM 1 to operate as P1 within the period of P1ACES-.
Write enable is enabled within the period of RWSTB-, and the data put on the data bus on the first port side is written to the SRAM 1 via the data bus input circuit 4.

In the read mode, the gate 8 enables the output of the data bus output circuit 5, and
The gate 11 enables the SRAM 1 to output within the period of P1ACES-, and when P1RESTB + changes to P1RWSTB- during the period of P1ACES-, 8 bits of the read data of the SRAM1 are latched by the data bus output circuit 5 and the data on the first port side is latched. It is output on the bus.

During the above operation period, the F / F5 keeps the positive phase output Q + at "1", so that the F / F2 outputs the negative phase output Q +.
When-is set to "1", this opens the gate 27 and F
"1" is input to the D terminal of the / F6, and the F / F2 sets the positive phase output Q + to "1" at the trailing edge of the clock CK where the F / F2 sets the negative phase output Q- to "1", and the second Bus connection control on the port side is performed in the same procedure.

[0039]

As described above, the dual port memory circuit of the present invention uses the random access memory which can be obtained at a low cost and has a large capacity,
Since the arbitration circuit gives priority to one of the memory access signals from the two CPUs, the processor can handle a large amount of data at a low price and can be easily expanded to an arbitrary capacity. There is an effect that a dual port memory circuit suitable for inter-communication can be provided.

[Brief description of drawings]

FIG. 1 is a circuit diagram of a random access memory, a bus connection control circuit and the like in a dual port memory circuit of the present invention.

FIG. 2 is a circuit diagram of an arbitration circuit in the dual port memory circuit of the present invention.

FIG. 3 is an operation time chart of each part of the arbitration circuit.

[Explanation of symbols]

 1 static random access memory (SRAM) 2 address bus input circuit 3 address bus input circuit 4 data bus input circuit 5 data bus output circuit 6 data bus input circuit 7 data bus output circuit 8 to 15 gates 21 to 31 gates F / F1 to F / F8 flip-flop

Claims (1)

[Claims] 1. A random access memory; a first port side address bus input circuit and a second port for respectively controlling connection between the address bus of the random access memory and the first port side address bus and the second port side address bus. Side address bus input circuit; first port side data bus input / output circuit and second port side data for respectively controlling connection between the data bus of the random access memory and the first port side data bus and the second port side data bus Bus input / output circuit; CPU on the first port side and second
In response to the memory access signal from the port side CPU, the first
A port side address bus input circuit and a data bus input / output circuit, and an arbitration circuit that preferentially operates one of the second port side address bus input circuit and the data bus input / output circuit. And a dual port memory circuit.