JPS6024980B2 - microcomputer - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION The present invention relates to a one-chip microcomputer and is directed to making it possible to take out the contents of its random access memory (RAM).

As is well known, the basic components of an electronic computer include a central processing unit (CPU), a storage device (memory) for storing instructions and processing data, and an input/output device (1/0).

The so-called microcomputers (abbreviated as microcomputers) that started with processors such as the Intel 4004 in the early 1970s are no exception, but the elements or systems called microcomputers are very small and mainly based on silicon M
Its greatest feature is that the above-mentioned computer building is realized using LSI (Large-Scale Integrated Circuit) related to OS technology.

In the early days of microcontrollers, the functions of a CPU were integrated into a single LSI.
What was realized above was mainly called a microprocessor or microcomputer, but today, due to improved integration, the memory part and even the 1/0 part are configured on one LSI. Using such LSIs, a simple system can be configured with one or a few LSIs and external components, resulting in a significant increase in cost and performance. It offers various difficult questions. One of them is data transfer.

A CPU and a RAM that stores its processing data are mounted on the same chip, and when the storage capacity of the RAM becomes large, the data stored in the RAM is taken out to the outside through the terminal pins of the chip, and the data is transferred from the outside to the RAM through the terminal pins. A request to write . For example, if you want to monitor data exchange between the microcomputer's internal RAM and an external 1/0 device, the information in a certain part of the microcomputer's internal RAM is stored in the CP.
Examples include wanting to see the information because it will serve as material for determining the operating status. A simple solution to this problem is for the CPU to input and output data to and from the RAM using the normal route. However, this increases the load on the CPU and reduces throughput. Also originally RA
In the M built-in microcontroller, the instruction sequence (program) is R.
There is also the problem that the operating state of the chip cannot be known from the outside because it is built into a fixed storage device such as an OM, and therefore it is difficult to make the CPU write to or negotiate a desired part of the RAM from the outside. Considering these points, RAM
It is preferable to use a DMA (direct memory access) method in which the contents are exchanged directly with the 1/0 device without going through the CPU. In a single-chip microcomputer, the number of pins is limited, and it is practically impossible to exclusively use a large number of terminal pins (eight in the case of an 8-bit parallel transfer system) for reading the contents of the RAM to the outside. Further, it is often necessary to read out the contents of the RAM during the development stage of a one-chip microcomputer, and it is not so necessary after completion. It is also uneconomical to allocate a large number of terminal pins to items that are only temporarily needed. The present invention has been made in view of the above, and is characterized by a central processing unit that performs logical and arithmetic operations, and a storage device that can store and issue data or instructions processed by the central processing unit. a DMA control circuit which is provided on the same chip and reads the contents of the storage device without going through the central processing unit during a period when the central processing unit is not accessing the storage device; and a control circuit that time-divisionally controls the boat so that the contents of the storage device read by the DMA control circuit can be output from terminal pins for exchanging data with an external device. be.

This will be explained in detail below with reference to the drawings. FIG. 1 shows a first embodiment of the present invention, in which 1 is a central processing unit (CPU) that performs logical and arithmetic operations, and 2 is a CPU that stores and displays data and instructions processed by the CPU. Random access memory (RAM), 4a, 4b,
...4n is a plurality of boats that exchange information with the outside, 3 is a buffer that stores the boat data, and these are on the same chip (semiconductor substrate) like a normal microcontroller. It will be installed.

The number of boats is the number of bits of data transferred in parallel (1
(number of bits in a word). In this example, a DMA control circuit 6 and a control circuit 7 for time-division use of ports are further provided on the same chip. The control circuit 7 has clocks T, , T2 and T.2 having the timing relationship shown in FIG. is inverted by the inverter 7a, and outputs a clock T, which is inverted by the inverter 7a, and outputs the clock T, which is inverted by the inverter 7a. , G2, and the clock signal line 5. To explain the operation, data to be sent to the outside is written to the buffer 3 through the intervention of the CPU, and is applied to one input terminal of the AND gate G of the boats 4a to 4n.

The data to be output by the DMA control circuit 6 and sent to the outside is applied from the RAM 2 to one input terminal of the AND gate G2 of the boats 4a to 4n, and then to the gates ○, .
A clock T,,T, is applied to the other input terminal of G2. The output terminals of these AND gates are led to OR gate G3 (not shown in 4b to 4n, but the same as 4a),
The output end of the gate G3 is connected to signal lines 8a to 8n. Therefore, during the day level of clock T, gate G. is opened, the data in the buffer 3 is sent out from the ports 4a to 4n, and DMA is requested via a path not shown, the control circuit 6 is activated, and when the RAM 2 is read, the data is transferred to the L level of the clock T. The CPU data and the DMA data are outputted to the outside by opening the gate G2 during the day level period of the clock T, and thus the CPU data and the DMA data are alternately outputted to the outside through the same port. Signal lines 8a to 8n
Clock T2 can be used to separate the CPU data and DMA data inside, and if data is captured at the rising edge of T2, it is DMA data, and if data is captured at the falling edge, it is CPU data.
It is data. In this example, the DMA of RAM2 is limited to an area corresponding to one specific word of the RAM.

This is sufficient for monitoring the CPU functions. When the RAM data to be sent to the outside by DMA is not one specific word of the RAM 2 but multiple words, the process is as shown in FIG. The counter is an address counter, and its count value becomes an address signal to access the RAM 2.

2a is a specific area of the RAM 2 that receives the access.

The timing at which the data in RAM2 is sent is during the day level period of the clock T to the same machine as in the case of Figure 1, but only one word (8 bits) can be sent at a time, and the address counter 0 indicates. Since the address is only for one word at one point in time, a plurality of words are processed using a plurality of day level periods of the clock T. When data thus sent out is received externally, it is necessary to identify whether the data belongs to address 1 of RAM 2 or not. For this purpose, a signal line 9 is added, and to this signal line are added the output of an OR gate G4 whose input terminal is connected to each bit of the address counter 10, and the output obtained by taking the NOR logic of the clocks T and T2. As a result of this NOR logic, specifically, the output of /Agate G5 is like the insect in FIG. 4, and is a clock whose output from the address counter is 0 during the RAM data transmission period, that is, when the DMA starts. If there is a clock T3, it is possible to easily know the RAM address of the data retrieved according to the contents of the address counter 10 externally by counting the rising edge of the clock T2. Figure 5 shows not only the RAM data sending circuit to the outside, but also the external RAM data sending circuit.
This figure shows the main part of a microcomputer that also includes a data writing circuit to AM.

In this example, the boats 4a to 4n have input lines with an even number of inverters G7 added to make them bidirectional, and also have RA input from the outside.
A boat 12 is provided to take in the address of M2. Although this boat 12 is simply shown as a rectangular block in the figure, it actually consists of a plurality of receivers, such as boats 4a, 4b, . . ., corresponding to the number of bits of the address signal. Also, line 1 to which the signal R/W that determines the write/read mode is input.
8 is provided, and the signal is applied to the RAM 2 and the gate ○6 which inhibits data transmission in the write mode. G,o,G,
2 is also a gate and is provided in the address signal input circuit from the outside to avoid conflict between CPU access and external access to RAM2. 16 and 17 are flip-flop circuits, and G3 is an AND gate, which outputs a signal L indicating "acceptance".

1, 12 are inverters.

Note that a force mMA control circuit 6 (not shown) is also provided in this circuit. In order to read the contents of the RAM 2 from the outside with this device, the address storing the desired data in the RAM is input through the port 12, and the R/W signal is turned on.

The R/W signal is inverted by the inverter 12 and becomes L, and the R/W signal
Set AM2 to lecture mode and open gates ○6 of boats 4a to 4n. When the CPUI accesses the RAM 2, the signal line 19 is set to L level, and when not accessed, the signal line 19 is set to H level. Assuming that it is not currently being accessed, the signal line 19 is at H level, which means that the inverter 1
．． is inverted and becomes L level, and the gates G,o,G. 2
open. Therefore, the address signal of the boat 12 enters the RAM 2 and accesses it. Further, the H level of the signal line 19 is sequentially input to the D-type flip-flops 16 and 17 by the clock T, and when the clock T is on the day and the Q output of the flip-flop 17 is on the day, the AND gate G3 receives the input as shown in FIG. Generates signal L. The external party knows from this signal T4 that the access has been accepted, and clocks T. L of
Receives RAM data sent during the level period. C.P.
When the UI accesses the RAM2, the signal line 19 is at L level, the gate GMG,2 is closed, and the address of the boat 12 is not input to the RAM2. Also, at this time, the L level is taken into the flip-flops 16 and 17, and the reception signal L is at the L level. FIG. 6 is a diagram explaining these situations. When addresses A, B, and C are sequentially input to the boat 12, the RAM data of the addresses are output with a delay of one clock. D(R) indicates this output. Note that time ti
In this case, a conflict occurs, and in this case, the RAM data at address B is sent out after the conflict is resolved. When writing, the address to the port 12 is also input as data to the ports 4a to 4n, and the R/W signal is set to L. If there is no conflict, these addresses and data are added to RAM2 and written. D(W) in FIG. 6 indicates that data A', B', . . . have been written to addresses A, B, . As explained above, according to the present invention, the contents of the memory can be quickly retrieved to the outside in parallel with multiple bits without increasing the number of input/output ports, and without bothering the CPU, which is extremely useful.

[Brief explanation of the drawing]

1, 3, and 5 are block diagrams showing embodiments of the present invention, and FIGS. 2, 4, and 6 are time charts for explaining the operation. In the drawing, 1 is a central processing unit, 2 is a storage device, 4a to 4n are boats, 6 is a DMA control circuit, and 7 is a boat time division control circuit. Figure 1 Figure 2 Figure 4 Figure 3 Figure 6 Figure 5

Claims (1)

[Claims] 1 A central processing unit that performs logical and arithmetic operations and a storage device capable of storing and reading data or instructions processed by the central processing unit are provided on the same chip, and the central processing unit has access to the storage device. A DM that reads the contents of the storage device without going through the central processing unit during a period when the storage device is not in use.
A control circuit and a port are set so that the contents of the storage device read out by the DMA control circuit can be outputted from a terminal pin through which the central processing unit exchanges data with an external device. A microcomputer characterized by comprising a control circuit that performs divided control.