JPS6197759A - Memory control system - Google Patents

Abstract

PURPOSE:To decrease the number of signal lines of an address bus by forming an extended address with a low-order address on the address bus and a high- order address latched by the 2nd latch circuit and storing the data on the data bus to a memory. CONSTITUTION:The appropriate addresses on high-order address bus 7 are latched previously as the high-order addresses by latch circuits 8 and 11. When data are transmitted to a memory 2 from a CPU1, a high-order address is delivered to the bus 7 from the CPU1 and compared with an output 8a of the circuit 8 by a comparator 9. Then a gate 10 is opened if said upper address exceeds the maximum address that can be shown on an address bus 4. Then the high-order address is delivered onto a data bus 8 and latched by a latch circuit 11 with the proper timing. The output 11a of the circuit 11 and the bus 4 form an extended address bus. While the gate 10 is never opened if the high-order address is less than said maximum address. Thus the same action is carried out as that of conventional bus constitution.

Description

DETAILED DESCRIPTION OF THE INVENTION [Field of Industrial Application] The present invention relates to a memory control system in which an upper address is transferred via a data bus only when the upper address changes to form an extended address together with the lower address.

[Conventional technology]

Figures 2 and 3 show the configuration of a conventional CPσ/memory, in which (1) is the CPU, (2) is the memory, and (8) is the CPU.
) is a data bus, (4) is an address bus, and (5) is an address/data multiplexer path, through which addresses and data are output in a time-division manner. (6) is an address latch circuit that latches the address on the address/data multiplexer bus (6), and (6) is its output, forming an address bus.

Next, the operation will be explained.

Figure 2 shows the configuration of a commonly used CPσ/memory, in which addresses and data output from the CPU (1) are transmitted separately via an address bus (4) and a data bus (8). , the data is stored in memory (2).

On the other hand, FIG. 3 uses a multiplexer bus that serves as both a data bus and an address bus, and the CPU (1) outputs addresses and data in a time-division manner and transmits them via the address/data multiplexer bus (5). This bus (6
) is latched by the address latch circuit (6), and the data on the multiplexer bus (5) is transferred to the memory (
2) [Problems to be solved by the invention] The conventional system is configured as described above, and in the case of the system shown in Figure 2, it is necessary to increase the number of signal lines as the number of addresses increases. However, in the case of the method shown in FIG. 6, there is a problem that the processing speed is slow.

This invention was made in order to solve such problems, and it is possible to reduce the number of signal lines of the address bus even when the address is expanded, and to reduce the delay in processing speed as much as possible. [Means for solving the problem] A memory control method according to the present invention has an address bus for transmitting lower addresses, an upper address bus for transmitting upper addresses, A first latch circuit that latches the upper address on the upper address bus, a comparator that compares the match or mismatch between the upper address latched by the first latch circuit and the upper address value on the upper address bus, and from the comparator. A gate that is opened in response to a mismatch output signal and transmits the upper address on the upper address bus via the data bus, and a second latch circuit that latches the upper address on the data bus, and the lower address on the address bus and The data on the data bus is stored in the memory by forming an extended address with the upper address latched by the second latch circuit.0 [Operation] In this invention, the data bus is Since it is used with address mapping, it is possible to reduce delays in processing speed as much as possible, and in addition to using the data bus as the upper address bus, it is also possible to reduce the number of signal lines for the address bus. Become.

〔Example〕

FIG. 1 shows an embodiment of the present invention, and the same reference numerals as in FIGS. 2 and 3 indicate the same or corresponding parts. (
7) is an upper address bus used only when the upper address changes, (8) is a latch circuit that latches the upper address above upper address (7), (8a) is its output, and (9) is the output (8a). A comparator circuit that compares and determines whether the upper address value on the upper address bus (7) satisfies a certain condition, in other words, whether the two signal values match or not; (9a) is its output, α0) is a gate whose opening/closing is controlled by the output (9a), and when gate α@ is opened, the upper address on the upper address bus (7) is connected to the data bus (8).
is output above. 0° C. is a latch circuit (11a) ij that latches the upper address on the data bus (3), and its output becomes the upper address bus and constitutes an expanded address bus together with the address bus (4).

Next, the operation will be explained. First, the upper address bus (
a) Latch the appropriate address on the circuit (8), C11)
In this state, data is transmitted from c p a (1) to memory (2). Then, there is a CPU on the upper address bus (7).
The upper address is output from (1). This upper address is determined by the comparator circuit (9) as the output of the latch circuit (8) (
8a), and if the two values do not match, in other words, if the condition of exceeding the maximum address that can be indicated on the address bus (4) is satisfied, the comparison circuit (9)
The output (9a) opens the goo (10), and the upper address on the upper address bus (7) is connected to the data bus (8).
At the same time, the latch circuit (8) latches the upper address value on the upper address bus (7).

Thereafter, the upper address on the data bus (8) is latched by the latch circuit α℃ at an appropriate timing.
The output (11a) and the address bus (4) constitute an extended address bus.

On the other hand, when the comparison circuit (9) judges that the above condition is not satisfied f4, that is, when the address output from the CPU (1) does not exceed the maximum address that can be indicated by the address bus (4), In this case, the gate signal remains closed, resulting in the same operation as the conventional path configuration shown in FIG.

Although not specifically explained in the above embodiment, the address bus (4) and the output (11a) of the latch circuit αη do not necessarily have to have the same number of signal lines.
They may be different from each other.

〔Effect of the invention〕

As explained above, according to this invention, the data bus is used as the upper address bus only when the upper address changes, so in the area where the upper address does not change, the operation is similar to the conventional method shown in FIG. Since the latch method is used only when the address is extended, the overhead is smaller than the conventional method shown in FIG. Also the second
This has the advantage that the number of signal lines can be reduced compared to the case where addresses are extended in the conventional method shown in the figure.

[Brief explanation of the drawing]

FIG. 1 is a block diagram of a memory control method showing an embodiment of the present invention, and FIGS. 2 and 3 are diagrams corresponding to FIG. 1 showing conventional memory and control methods, respectively. (1)... c P U (2)... Mesori (8
)...Data bus (4) Contention/Address bus (γ) -
Reference address bus (8), C11) Latch circuit (9) Comparison circuit (10) Gate Note that in each figure, the same reference numerals indicate the same or equivalent parts.

Claims (1)

[Claims] An address bus for transmitting a lower address, an upper address bus for transmitting an upper address, a first latch circuit that latches the upper address on the upper address bus, and an upper address latched by the first latch circuit and a higher address bus on the upper address bus. a comparator that compares the match or mismatch with the upper address value of
It includes a gate that opens in response to a mismatch output signal from the comparator and transmits the upper address on the upper address bus via the data bus, and a second latch circuit that latches the upper address on the data bus. A memory control method characterized in that a lower address and an upper address latched by a second latch circuit constitute an extended address and data on a data bus is stored in a memory.