JP2906805B2 - Memory sharing type multiprocessor system - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a tightly coupled multiprocessor system having a shared memory.

[0002]

2. Description of the Related Art In a multiprocessor system, it is necessary for processors to mutually exchange information necessary for processing to proceed. From the viewpoint of a coupling method for realizing such inter-processor communication, it can be broadly classified into a tightly-coupled multiprocessor and a loosely-coupled multiprocessor.

A tightly coupled multiprocessor can be realized by providing an interconnection network between a plurality of processors and a memory, as shown in FIG. As the number of processors increases, contention for access to shared memory (conten
) occurs, and the access becomes sequential and the efficiency of parallel processing decreases.

As shown in FIG. 9 (b), loosely coupled multiprocessors have their own local memory (local memory).
y) and does not have global shared memory. Communication between processors is performed via a high-speed input / output port. In a loosely coupled multiprocessor, contention in a memory does not occur, but if each processor relays communication, a relay load becomes a problem.

[0005] In these shared multiprocessor systems, each processor operates while sharing a main memory, and the main memory can be directly accessed from each processor. But,
If the entire memory space is completely shared, access traffic to the main memory increases, causing a bottleneck and deteriorating performance.

For this reason, the following contrivance has been made as shown in FIG. Each processor is provided with its own local memory that does not conflict with other processors, and the shared area is limited to a part. The shared memory space is divided and each partial space is allocated to each processor.

[0007]

In such a system, when each processor accesses the shared space, an arbiter circuit for performing arbitration is required to avoid contention with other processors. If the number of processors (PE) is small, there is not much problem.

SUMMARY OF THE INVENTION The present invention has been made in view of the above problems, and has as its object to provide a shared memory type multiprocessor system in which arbitration is easy and the system can be easily expanded.

[0009]

FIG. 1 is a block diagram showing the principle of the present invention. The present invention relates to a shared memory multiprocessor system including a plurality of processor units each including a partial space memory 1 obtained by dividing a shared memory space and a processor 2, wherein a gate 3 is provided between each processor unit, and a gate 3 is provided between the processor units. An arbitration circuit 4 for controlling the output of a plurality of processors 2 on one side of the gate 3, for example, the right side in FIG. , Gate 3
A logic circuit for converting the other partial space memory use request signal of all the processors 2 on the other side, for example, the left side, into one use request signal, for example, an output of a logical sum is inputted to each arbitration circuit 4 It is.

Further, when the use request signal is inputted repeatedly, the use request is responded to in a preset priority order.

[0011]

The arbitration circuit 4 includes n processor units and n-1 arbitration circuits 4 provided therebetween.
When referring to the partial memory 1 between the processor units i, j (1 <i <j <n), only the gate 3 between i, j is opened.

[0013]

FIG. 1 shows the case of two processor units, but a desired processor unit can be connected by adding them to the left and right. In the case of FIG. 1, when each processor refers to its own memory 2, the arbitration circuit 4 closes the gate 3 and the other memory 2
, The gate 3 is opened.

FIG. 2 shows the gate opening / closing logic shown in FIG. lock-A and lock-B are access requests to the partner memory, where 1 is for requests and 0 is for no requests. In the case of (1, 1), the priority is granted to the processor 2 on the left side, which is the same as (1, 0).

When both the left and right processors 2 issue a request for referring to the memory 1 of the other party, the arbitration circuit determines in advance the priority order to be used in the case of contention. In the case of FIG. 1, for example, priority is given to the processor 2 on the left side,
First, the processor 2 on the left refers to the memory 1 on the right, and then the processor 2 on the right refers to the memory 1 on the left.
This is the same when there are three or more processor units.
For example, the highest priority is given to the processor 2 at the left end, and the priority is sequentially reduced as going to the right.

Each arbitration circuit 4 receives the logical sum of the use request signals of all the processors 2 on the right side and the logical sum of the use request signals of all the processors 2 on the left side. In this way, the number of processor units can be easily increased.

When the memory 2 is referred to by the processor 2 of i and j, only the gate 3 between the processors 2 of i and j is opened, the gate 3 between 1 and i, and the gate between i and n. By closing 3, the processor 2 in the closed section can access its own memory 1.
As a result, the influence on the other processor 2 caused by one processor 2 referring to the other memory 1 can be minimized.

[0018]

Embodiments of the present invention will be described below with reference to the drawings. FIG. 3 shows a configuration diagram of the first embodiment of the present invention. 1 is a partial space memory obtained by dividing the shared memory space, 2 is a processor, 3 is a gate enabling input / output between the partial space memories 1, and 4 is an arbitration circuit for controlling opening and closing of the gate 3. Input request signal. Reference numeral 5 denotes a gate provided for each processor 2.

Next, the operation will be described. FIG. 4 shows the gate opening / closing logic. In FIG. 4, lock-A, lock-B
Are use request signals to other partial space memories 2 output from PE-A and PE-B, respectively. 0 indicates no lock signal and 1 indicates lock signal. When the lock signal is output from both PE-A and PE-B, in the case of (1, 1), P
The priority is granted to EA, so the gate opening / closing is the same as in (1, 0). In the case of (1,1), MEM of PE-A
PE-B is ME only after access to
Cannot access M-A.

Next, a second embodiment will be described. FIG. 5 is a diagram showing the configuration of the present embodiment. This embodiment is similar to the first embodiment shown in FIG.
Example: memory MEM-C, gate GATE-F, processor
PE-C is added. For this purpose, GATE-B and arbitration circuit AB-B are added. AB-A has a lock signal from PE-A on the left side and PE-B and PE on the right side.
The logical sum of the -C lock signal is input. AB-B receives the logical sum of the lock signals of PE-A and PE-B on the left side and the lock signal from PE-C on the right side.

Next, the operation will be described. FIG. 6 shows the gate opening / closing logic of this embodiment. Priority is PE-A, PE-
B and PE-C are provided in this order. So (0,1,0)
And (0,1,1) are in the same gate open / close state. (1,0,0), (1,0,1), (1,1,0),
(1,1,1) are in the same gate opening / closing state. Note that GA
TE-E is determined by the logical product of the lock signals of both GATE-Ea and GATE-Eb. For example, when (1, 0, 0), GATE-E
a is closed and GATE-Eb is open, so GATE-E is closed x
Open = closed.

The opening and closing of the gate is based on a signal of 1 bit. If this is made into a plurality of bits, more complicated opening / closing processing becomes possible. For example, in the example shown in FIG.
-When A accesses MEM-B, GATE-B is not relevant
Open and GATE-F closed. For this reason, the PE-C cannot access its own memory MEM-C, but can prevent such a situation and control to open or close the gate only in the use range.

Next, a third embodiment will be described. FIG. 7 shows the configuration of this embodiment. This embodiment is different from the second embodiment shown in FIG. 5 in that a memory MEM-D, a gate GATE-G, and a processor PE-
D and gate GATE-C, arbitration circuit AB-C
Is added. In accordance with this, PE-C and PE-D
OR gate for transmitting the ck signal to the left side, PE-A, PE-B,
An OR gate for transmitting the PE-C lock signal to the right side is also added.

Next, the operation will be described. The arbitrage circuits AB-A, AB-B and AB-C are connected to the gates GATE-A and GA in accordance with the same logic as shown in FIG.
It controls TE-B and GATE-C. Gate GATE-D, GA
TE-G opens and closes according to inputs a and b, and gates GATE-E,
GATE-F opens and closes according to the logical product of inputs a and b.

For example, consider a case where PE-B wants to access a memory (for example, MEM-D) belonging to another PE. PE-B
Outputs the lock signal to the OR gate. In the OR gate, the lock signals from PE-C and PE-D are not active, but since the lock signal from PE-B has changed to active, the lock signal is transmitted to the arbitration circuit AB.
-A, Output to gate GATE-D. In GATE-D, the gate is closed by the input of the lock signal, and the bus of the memory MEM-A is opened. The arbitration circuit AB-A is PE-A
Although the lock signal is not issued, GATE-A is opened because PE-B has issued the lock signal.

Similarly, GATE-E operates by the outputs of PE-A and OR gate, but GATE-E, PE-A, PE-C, PE-A
D does not output the lock signal, so open the gate and PE-
The address of B is output to the memory bus. Similarly, GATE-B and GATE-C open the gate, and GATE-F and GA
TE-G closes the gate and the shared memory bus passes only the signal of PE-B, so that PE-B can access the memory MEM-D.

In this example, the case where the lock signal is performed by one bit has been described. For this reason, GATE-A, which is unnecessary for PE-B to access MEM-D, is closed and GATE-D is closed. This can be prevented by performing the lock signal with a plurality of bits as described above.

Next, a fourth embodiment will be described with reference to FIG. This embodiment is different from the third embodiment shown in FIG.
E, gate GATE-I, processor PE-E and gate GATE-
H, in which an arbitration circuit AB-D is added. Accordingly, an OR gate for transmitting the lock signal of PE-D and PE-E to the left side, and an OR gate for PE-A, PE-B, PE-C, and PE-D.
Increase the OR gate that transmits the lock signal to the right.

The operation of the arbitration circuit AB-C, AB-D and the gate is performed by an OR gate.
It is only necessary to generate signals for controlling GATE-H and GATE-I from the lock signal of PE-E and the signals from PE-A to PE-D. As described above, according to the present invention, a shared memory type multiprocessor system can be configured without providing an arbitration circuit for integrally controlling all PEs.

[0030]

As is apparent from the above description, the present invention has a configuration in which a subspace memory and a processor unit are horizontally connected via an arbitration circuit, and requires an arbitration circuit for unified control of all processors. Therefore, the control is simple and the unit can be easily added.

[Brief description of the drawings]

FIG. 1 is a principle block diagram of the present invention.

FIG. 2 is a diagram showing a gate opening / closing logic of FIG. 1;

FIG. 3 is a circuit diagram of a first embodiment of the present invention.

FIG. 4 is a diagram showing gate opening / closing logic of the first embodiment.

FIG. 5 is a circuit diagram of a second embodiment.

FIG. 6 is a diagram showing gate opening / closing logic according to the second embodiment.

FIG. 7 is a circuit diagram of a third embodiment.

FIG. 8 is a circuit diagram of a fourth embodiment.

FIG. 9 is a diagram illustrating a tightly coupled and loosely coupled multiprocessor.

FIG. 10 is a diagram illustrating an example of a conventional tightly-coupled multiprocessor.

Claims (3)

(57) [Claims] 1. In a shared memory multiprocessor system comprising a plurality of processor units each comprising a partial space memory (1) obtained by dividing a shared memory space and a processor (2), a gate (3) is provided between each processor unit. An arbitration circuit for controlling the gate (3) is provided with (4), and each arbitration circuit (4) has one of the gates.
Use of other partial space memory of multiple processors (2) on the side
Circuit output for converting a use request signal into one use request signal
And a plurality of processors (2) on the other side of the gate
The other partial space memory use request signal is
A shared memory type multiprocessor system characterized in that it is configured to receive a logic circuit output to be input. 2. The memory sharing type multiprocessor system according to claim 1, wherein when the use request signal is inputted repeatedly, the use request is responded to in a preset priority order. 3. An arbitration circuit (4) comprising n processor units and n-1 arbitration circuits (4) provided therebetween.
When referring to the partial memory (1) between the processor units of i, j (1 <i <j <n), only the gate (3) between i and j is opened. The multiprocessor system according to claim 1, wherein: