JPH04113444A - Bidirectional ring bus device - Google Patents

Abstract

PURPOSE:To ensure the optimum network communication efficiency by giving the information on the number of packaged processors of a parallel, processing system, the self-node address information, and the address information on the processor of the transfer destination to each transfer destination deciding circuit of communication nodes and attaining self-routing. CONSTITUTION:A transfer destination deciding circuit 101 consisting of a transfer destination decision table 200 and an inverting circuit 201 is provided in each communication node. Then the information on the number of packaged processors is given to the circuit 101 together with the self-address information, and the address information on the processor of the transfer destination. So that the circuit 101 can perform the self-routing. Thus the communication efficiency of a network is optimized with no change of the hardware nor a program even though the number of processors is increased or decreased (expanded or reduced).

Description

DETAILED DESCRIPTION OF THE INVENTION (Field of Industrial Application) The present invention relates to a bidirectional ring toss that interconnects a plurality of processors in a parallel processing system that executes parallel processing using a plurality of processors. be.

(Prior Art) A bidirectional ring bus system is available as a means for connecting parallel processing computers. The bidirectional ring bus method is, for example, a method in which the nearest neighbor network (page 129 of this document) disclosed in the document ``Switching Network for Parallel Computers'' by Kyoritsu Shuppan Co., Ltd. is limited to a one-dimensional connection relationship. be. FIG. 5(a) shows an example in which eight processors 2 (hereinafter also referred to as PEs) 2 are coupled in a bidirectional ring bus system.

PE#O to PE#7 connect to a left-rotating ring bus 20 and a right-rotating ring bus 30 via their respective communication nodes 1.
are mutually connected. When mutual data communication is performed between each PE, the communication data is routed by selecting a left-rotating ring bus or a right-rotating ring bus, but which ring bus to select is determined in advance by hardware in the communication node 1. This was done either by the program control of each PE2 or by program control of each PE2. For example, when transferring communication data from PE#3 to each PE, PE#4, PE#5, PE
The communication node l is configured to selectively route the left-rotating ring bus 20 to PE#6 and PE#7, and the clockwise-rotating ring bus 30 to PE#01, PE#1, and PE#2. Hardware or program controlled during PE2.

(Problem to be Solved by the Invention) By the way, the case where the number of processors is reduced from the 8 processor configuration indicated by # in FIG. 5(a) to 4 (from PE#O to PE#3) is shown in FIG. b) Consider as pay PE#0 to PE'#3
is reconnected as a new neighboring PE. PE#3
When transferring data from PE#01 to PE#1 and PE#2, select the right-rotating ring bus 30 in FIG. The boarding bus 20 will not be selected. However, from PE#3 to PE#
For transfer of communication data to PE 0, selecting the left-rotating ring bus 20 for routing reduces the distance between PEs, resulting in the best communication efficiency. As described above, conventional bidirectional ring buses have the disadvantage that if you want to expand or contract the system scale by freely increasing or decreasing the number of processors, you cannot optimize the communication efficiency of the network unless you change the hardware or program. Ta.

(Means for Solving the Problems) The present invention eliminates the above drawbacks, and provides a method for configuring a parallel processing system in which a plurality of processors are connected via a bidirectional ring bus. In a parallel processing computer system including connected communication nodes, the communication nodes are connected to form a bidirectional bus using two ring-shaped unidirectional buses,
Each of the communication nodes is provided with a transfer destination determination circuit, and self-routing is performed by providing this transfer destination determination circuit with information on the number of implemented processors of the parallel processing system, self-node address information, and address information of the transfer destination processor. This is a bidirectional ring bus device designed to allow

(Operation) According to the present invention, as described above, a transfer destination determination circuit is provided in the communication node, and self-routing is performed by providing information on the number of installed processors, self address information, and address information of the transfer destination processor to this circuit. Even if the number of processors increases or decreases (expansion or reduction),
Network communication efficiency can be optimized without changing hardware or programs.

(Embodiment) FIG. 1 is an internal configuration diagram of a communication node showing an embodiment of the present invention, showing a first communication node, a second communication node, and a third communication node connected by a bidirectional ring bus, The detailed configuration of each communication node is shown as a first communication node.

This first communication node communicates with PEtIn by receiving communication data 10 of PEtIn from the Pin terminal and outputting communication data 16 to the Pout terminal. In addition, this first communication node is connected to a second communication node adjacent to the left and right and a third communication node.
Communication between communication nodes is performed by receiving communication data 20 from the L1n terminal and outputting communication data 21 to the Lout terminal. Furthermore, communication for clockwise rotation is performed by receiving communication data 30 from the R1n terminal and outputting communication data 31 to the Rout terminal.

Now, the first communication node of the present invention has a left input buffer 102 and a right large buffer 103 that store the communication data IO of PE#n input from the Pin terminal, and determines the storage (transfer) destination of the communication data IO. Transfer destination determination circuit 101
, a left output buffer 108 and a right output buffer 109 that respectively store communication data 20 and 30 input from the Lln or R1n terminal to PE#n, and PE#n input from the Lln or f or R1n terminal. A left intermediate buffer 10 stores communication data 20 and 30 to the PE, respectively.
5 and right intermediate buffer 107, and left output selector 104 and right output selector 1 for through-transferring communication data 20 and 30 or communication data 17 and 18 from left input buffer 102 and right input buffer +03.
0[i, and a left input control circuit and a right input control circuit that respectively control input light of the communication data 20 and 30. All communication data 10, 20, and 30 are the contents to be communicated plus transfer destination address information, and the field structure thereof is shown in FIG. The self-address information shown by phantom lines in FIG. 2 may be stored in a register within each communication node, as will be described later.

This allows each communication node to have a self-routing function.

The communication procedure for communication data input from each input terminal will be explained in detail below.

■Procedure for transferring communication data from the pin terminal The transfer destination determination circuit 101 receives transfer destination address information II in the communication data 10 from the pin terminal, receives information on the number of installed processors 12 from the outside, and further receives information on the number of installed processors 12 from the outside. The self-address information 13 stored in the register 2 surrounded by the image line, or the self-address information 13 in the communication data 10
(These are the same information) are input. If the communication data is to be transferred to a destination PE through the left-rotating ring bus, the left enable signal I4 is activated and the communication data 10 is stored in the friend buffer 102. The communication data 10 stored in the friend's cover sofa +02 is transferred to the third communication mate via the left output selector 104 and the Lout terminal. Further, if the communication data is to be transferred to a PE with a transfer destination through the rightward ring bus, the right enable signal J5 is made active and the communication data IO is stored in the right input cover 103. The communication data 10 stored in the right input cover sofa 103 is transferred to the second communication node via the right output selector IO[i and the Rout terminal.

■Transfer procedure for communication data from the Lln terminal The left input control circuit 110 transfers the communication data 20 from the second communication node to the Lln terminal.
received from the in terminal, compares some communication data in this communication data 20, that is, transfer destination address information 22, and the self-address information 13, and compares both address information 22, I
3 match, the communication data 2o is stored in the left output buffer 108, and if both the address information 22.13 do not match, it is recognized as the communication data passing through the first communication node and the left This communication data 2o is simply transferred to the third communication node via the output line 21 via the intermediate buffer 105 or the left output selector +04 and the Lout terminal. Furthermore, the communication data 2o stored in the left circular cover sofa 108 is transferred to PEtln through the Pout terminal.

■Procedure for transferring communication data from the R1n terminal The right input control circuit 111 transfers the communication data 30 from the third communication node to the R1n terminal.
1n terminal, compares some communication data in this communication data 30, that is, transfer destination address information 32, and the self-address information 13, and compares both address information 32.1.
3 match, the communication data 30 is stored in the left circular cover sofa 109, and if both the address information 32 and I3 do not match, it is recognized as the communication data passing through the first communication node, and the communication data 30 is stored in the left circular cover sofa 109. This communication data 30 is simply transferred to the second communication node via the output line 31 via the intermediate buffer 107 or the right output selector 10B and via the Rout terminal. Furthermore, the communication data 20 stored in the left output buffer 109 is transferred to PE#n through the Pout terminal.

FIG. 3 shows a specific configuration of the transfer destination determining circuit +01 as an example. The circuit +01 is the transfer destination determination table 20
0 and an inversion circuit 201, and self-address information 13
Information on the number of implemented processors] 2 and forwarding address information 11
and receives the left enable signal 14 and right enable signal 1.
Outputs 5. The transfer destination determination table 200 is, for example, RO.
It can be realized by M (leat only), receives the self address information 13, the number of installed processors information 12, and the transfer destination address information 11, and outputs the left enable signal 4. The inverting circuit 201 receives the left enable signal 14;
A right enable signal 15 having the inverted logic is output. FIG. 4(a) shows an example of the contents of the transfer destination determination table 200 written when the number of installed processors is eight. The operation of this transfer destination determining circuit +01 will be explained below. In FIG. 4(a), for example, when the self address information 13 is #3, and when the transfer destination address information 11 is #4, #5, #6, or #7, the left enable signal 14 is 1, and the inverting circuit 201 The enable signal 15 becomes 0, the left enable signal 14 in the first communication node in FIG. output to the bus. Similarly, self address information I3 is #
3, if the forwarding address is #0, #1, #2,
The left enable signal I4 becomes 01, the output right enable signal 15 becomes 1 by the inversion circuit 201, the left enable signal 14 in the first communication node in FIG. Communication data IO is stored in the right large buffer 102 and output to the clockwise rotating ring bus. Also, Section 4(b)
2 shows an example of the contents of the transfer destination determination table 200 written when the number of implemented processors is 4, but the operation is the same. In this way, if the communication node configuration of the present invention is adopted, in a parallel processing system connected by a bidirectional ring bus, the transfer destination determination table 200 for the number of processors scheduled to be increased or decreased can be stored in a ROM, for example, and the optimal Communication channels can be routed.

(Effects of the Invention) According to the present invention, data communication between each processor can be performed by taking into account the number of installed processors, self-address information, and transfer destination address information in each communication node, and is capable of self-routing the optimal communication path, thereby maximizing the system as a whole. Fig. 4 is a diagram of the internal configuration of the communication mate that is effective in bringing out communication efficiency. Fig. 0 is a diagram of the forwarding destination determination circuit according to an embodiment of the present invention. Fig. 0 is a diagram of the field configuration of communication data. Figures 5(a) and 5(b) are diagrams explaining the contents of the transfer destination determination table. Figures 5(a) and 5(b) are configuration diagrams of parallel processors. Figure 5(a) shows eight processors, and Figure 5(b) shows four FIG. 2 is a configuration diagram of a parallel processor in which processors are each coupled via a bidirectional ring bus.

There is fruit.

[Brief explanation of drawings]

FIG. 1 is a ring bus device (b) showing an embodiment of the present invention. 4 unit configuration Parallel processor configuration diagram Figure 5

Claims (1)

[Claims] In a parallel processing computer system including a plurality of processors and a communication node connected to each of the processors, the communication nodes are connected to form a bidirectional bus by two ring-shaped unidirectional buses. Each communication node is provided with a transfer destination determination circuit, and self-routing is performed by providing this transfer destination determination circuit with information on the number of implemented processors of the parallel processing system, self-node address information, and address information of the transfer destination processor. A bidirectional ring bus device characterized by: