JPH05303558A - Method and device for message packet routing of array processor - Google Patents

Abstract

PURPOSE:To freely set routing by a program and to broadcast data from a transmission-source processor to plural processors by a single message communication by rewriting a routing table by the array processor. CONSTITUTION:Each of unit processors which are connected by four links in a mesh shape consists of an arithmetic processor 21, a processor port 22, 1st-4th communication ports 23-26, a control circuit 27, and the routing table 28. The routing table 28 can be set and altered by the arithmetic processor 21. Namely, bits for setting whether or not transfer to a transfer destination is performed are assigned in the routine table 28, and the route of message transfer can be set or changed by the program before or in program execution. Therefore, a local increase in traffic depending upon application software can be evaded.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to an array processor message packet method and apparatus for performing interprocessor communication by link-linking processors.

[0002]

2. Description of the Related Art Conventionally, as a method of realizing an array processor, 1) a method of performing only communication between adjacent processors,
2) There is a method of realizing communication between remote processors using a router.

Among these, in the method of performing communication only between adjacent processors, the amount of hardware required for processor communication is relatively small, but when performing communication between remote processors, it is on the path from the sending processor to the receiving processor. Since communication between adjacent processors is repeated between each processor, the communication time and the load on each processor on the communication path become problems. For an array processor that performs communication only between adjacent processors, S.M. Y. Ku
ng, “Wavefront Array Proce
sorss-Concepts to Implement
station ”, IEEE Computer, Ju
ly 1987, pp-18-33. On the other hand, in the method using a router, the amount of hardware required for inter-processor communication is large, but since communication is performed from the sending processor to the receiving processor via the router, the communication time is relatively short, and communication to other processors is relatively small. Load does not matter either.

The routing method in the method using the router is determined depending on the connection form of the processors. For example, in the two-dimensional mesh connection method, routing is performed by designating the number of steps (hop number) in the east-west direction and the number of steps (hop number) in the north-south direction. W. J. Da
lly, "A VLSI Architecture
or Concurrent Data Strucc
"Tures", Kluwer Academic Pr
Section 5.3.3 of Ess, 1987 describes the routing system described above.

[0005]

However, since the route used is fixed in the conventional routing method,
Depending on the application, the traffic increases in one route, which may cause a communication bottleneck and hinder the parallelization of processing. Also, when data is broadcast to a plurality of processors, communication must be performed for each destination processor.

An object of the present invention is to provide a routing method and apparatus for an array processor in which routing can be freely set by a program by a program and data can be broadcast from a source processor to a plurality of processors by a single message communication. To do.

[0007]

SUMMARY OF THE INVENTION A message packet routing method for an array processor according to the present invention is an array processor which comprises a plurality of arithmetic processors and a low-dimensional mesh interconnection network for communicating between the processors. , A method of routing a message packet from a source processor to one or more destination processors, wherein one of a plurality of connection links generated from or connected to the arithmetic processor for each arithmetic processor in the network Means for transferring the message packet sent from the device to one or more destinations specified by a plurality of connection links or arithmetic processors, and one or more relays for transferring the message packet from the address information in the message packet. A routing information storage means for designating a network processor or an arithmetic processor, and enabling the setting of the routing information storage means by the arithmetic processor, so that each processor in the network can respond to one or more designated destination processors. The feature is that the message packet can be sent by an arbitrary route.

A message packet routing device for an array processor according to the present invention comprises a plurality of arithmetic processors,
An array processor configured with a low-dimensional mesh-like interconnection network for communicating between processors, which is a device for routing a message packet from a source processor to one or more destination processors, For each arithmetic processor, an input / output unit for the arithmetic processor, an input / output unit for a plurality of connected links, and one or more designated message packets sent from the arithmetic processor or one connected link At least a mutual connection network for transferring to a plurality of links or arithmetic processors and a routing table for designating one or a plurality of links or arithmetic processors for sending a message packet from address information in the message packet are provided. Allowing the writing of the routing table by the arithmetic processor.

[0009]

The principle of the present invention will be described below. According to the message packet routing method of the present invention, the destination address information added in the message packet is used to access the routing table to obtain the transfer destination information. Since the routing table has bits assigned to all possible transfer destinations (connection links and processors) to set whether or not to transfer, it is possible to transfer to multiple links or arithmetic processors.

Further, since the routing table can be rewritten by the arithmetic processor, it is possible to set and change the route of message transfer by the program before or during the execution of the program. This makes it possible to avoid a local increase in traffic depending on the application.

Further, when sending one message packet to a plurality of unit processors, one address is assigned to a group of a plurality of processors, and a message transfer to each processor is made to a corresponding address in the routing table of each unit processor. This is possible by setting the value that realizes the route.

[0012]

Embodiments of the present invention will now be described with reference to the drawings.

FIG. 1 is an embodiment of the present invention and shows an array processor in which unit processor nodes connected to four links are connected in a two-dimensional grid. FIG. 2 shows the configuration of a unit processor node. The unit processor includes an arithmetic processor 21, a processor port 22, a first communication port 23, a second communication port 24, a third communication port 25,
It comprises a fourth communication port 26, a control circuit 27 and a routing table 28.

The first communication port 23, the second communication port 24, the third communication port 25, and the fourth communication port 26 receive message packets sent from other connected unit processor nodes, The destination address information in the message packet is extracted and sent to the control circuit 27. The processor port 22 extracts the destination address information of the written message packet from the arithmetic processor and sends it to the control circuit 27.

The control circuit 27 draws the routing table 28 according to the destination address sent to transfer the first communication port 23, the second communication port 24, the third communication port 25, and the fourth communication port 26 to be transferred. A message transfer control signal is sent to either or the processor port 22. At this time, the routing table shows the first communication port 23, the second communication port 24, and the third communication port 2.
5, the fourth communication port 26, the processor port 22 5
One address word is made up of 5 bits in which 1 bit is assigned to each destination, and the memory is readable and writable having an address space obtained by adding a fixed number of additional numbers to the number of processors. The routing table 28 can be set and changed by the arithmetic processor 21.

The first communication port 23, the second communication port 24, the third communication port 25 and the fourth communication port 26 are also adjacent to which the message packet sent when receiving the message transfer control signal is connected. Send to unit processor node. When the processor port 22 receives the message transfer control signal, the processor port 22 receives and stores the sent message so that the arithmetic processor 21 can read it.

FIG. 3 shows an example of message transfer. Figure 3
Shows the array processors connected in the two-dimensional grid pattern shown in FIG. In FIG. 3, P in each unit processor indicates an arithmetic processor. The array processor shown in FIG. 3 includes a first unit processor 31, a second unit processor 32,
Third unit processor 33, fourth unit processor 3
The fourth unit processor 35, the sixth unit processor 36, the seventh unit processor 37, the eighth unit processor 38, and the like.

FIG. 4 shows the routing table of each processor. In FIG. 4, the column of P is a processor, the column of N is upward, the column of E is rightward, the column of S is downward, and the column of W is a bit that specifies transfer to the left.

The message packet sent from the arithmetic processor of the first unit processor 31 is sent to the second unit processor 32 by the value E of the address 7 in the routing table of the first unit processor 31, and is sent to the second unit processor 32. Then, the value E of the address 7 in the routing table of the second unit processor 32 is sent to the third unit processor 33. In the third unit processor 33, the value of the address 7 in the routing table of the third unit processor 33. S is sent to the seventh unit processor 37 by S, and in the seventh unit processor 37, the value P of the address 7 in the routing table of the seventh unit processor 7 is sent.
7th unit processor 3 which is a destination processor
Written to 7 processor ports. The path of such message transfer is determined by the setting of the routing table of each unit processor shown in FIG.

FIG. 5 shows another example of message transfer.
FIG. 5 shows an array processor having the same configuration as in FIG. Further, FIG. 6 shows a routing table corresponding to FIG. 1
One message packet from the first unit processor 31 to the fourth unit processor 34, the fifth unit processor 3
5, when sending to the sixth unit processor 36, one address 1 for the group of the fourth unit processor 34, the fifth unit processor 35, and the sixth unit processor 36
7 is assigned, and as shown in FIG. 6, a value that realizes a message transfer route to each processor is set in the corresponding address 17 of the routing table of each unit processor.

The message packet sent from the arithmetic processor of the first unit processor 31 is sent to the second unit processor 32 and the fifth unit processor 35 by the value ES of the address 17 in the routing table of the first unit processor 31. And the second unit processor 32
Then, according to the value E of the address 17 in the routing table of the second unit processor 32, the third unit processor 3
3 is sent to the third unit processor 33, and the address 1 of the routing table of the third unit processor 33 is sent to the third unit processor 33.
The value E of 7 is sent to the fourth unit processor 34, and in the fourth unit processor 34, the fourth unit processor 3
It is written to the processor port of the fourth unit processor 34, which is the destination processor, by the value P of the address 4 in the routing table of No. 4.

At the same time, in the fifth unit processor 35, the value PE of the address 17 in the routing table of the fifth unit processor 35 is written in the processor port of the fifth unit processor 35 which is the destination processor. This is sent to the sixth unit processor 36 at the same time. In the sixth unit processor 36, the value P of the address 17 in the routing table of the sixth unit processor 36 is sent.
By the sixth unit processor 3 which is the destination processor
Written to 6 processor ports.

As described above, the first unit processor 31 to the fourth unit processor 34 and the fifth unit processor 3 are set by setting the routing table shown in FIG.
5, are transferred to the sixth unit processor 36 at the same time.

[0024]

As described above, according to the present invention, by rewriting the routing table in the array processor, a message packet of an arbitrary route can be sent, and a message can be simultaneously sent from a unit processor to a plurality of unit processors. It is possible to send packets.

[Brief description of drawings]

FIG. 1 is a diagram showing an embodiment of a first invention,

FIG. 2 is a diagram showing a configuration of a unit processor,

FIG. 3 is a diagram showing an example of message transfer,

FIG. 4 is a diagram showing a routing table of each unit processor in the example of FIG. 3;

FIG. 5 is a diagram showing another example of message transfer;

FIG. 6 is a diagram showing a routing table of each unit processor in the example of FIG. 5;

[Explanation of symbols]

 21 arithmetic processor 22 processor support 23 first communication port 24 second communication port 25 third communication port 26 fourth communication port 27 control circuit 28 routing table 31 first unit processor 32 second unit processor 33 third 3 unit processor 34 4th unit processor 35 5th unit processor 36 6th unit processor 37 7th unit processor 38 8th unit processor

Claims (2)

[Claims] 1. An array processor comprising a plurality of arithmetic processors and a low-dimensional mesh-like interconnection network for communicating between the processors, wherein a message packet is routed from a source processor to one or more destination processors. A message packet sent from one of a plurality of connection links generated from or connected to the arithmetic processors to each arithmetic processor in the network. Means for transferring to one or more destinations specified from the inside, and routing information storage means for specifying one or more links or arithmetic processors for transferring the message packet from the address information in the message packet. A method of routing a message packet, wherein a message packet can be sent from each processor in the network to one or more designated destination processors by an arbitrary route by enabling the setting of the routing information storage means by a sessa. 2. An array processor comprising a plurality of arithmetic processors and a low-dimensional mesh-shaped interconnection network for communicating between the processors, wherein a message packet is routed from a source processor to one or more destination processors. A device for performing, for each arithmetic processor in the network, an input / output unit for the arithmetic processor, an input / output unit for a plurality of connected links, and an arithmetic processor or one connected link. Specifies an interconnection network that transfers incoming message packets to specified one or more links or arithmetic processors, and one or more links or arithmetic processors that send the message packets from the address information in the message packets. A routing device for message packets, which comprises at least a routing table and enables the arithmetic processor to write the routing table.