JP2003058489A - Semiconductor integrated circuit - Google Patents

Abstract

PROBLEM TO BE SOLVED: To provide a semiconductor integrated circuit capable of reducing the number of wires and shortening access time without increasing design time or the processing load of an MPU. SOLUTION: The semiconductor integrated circuit is provided with common buses 20, 30 for connecting a control part 10 to other function parts 11 to 14 and transmitting signals of respective parts and common interface parts 10a to 14a respectively built in the control part 10 and the other function parts 11 to 14 and transferring signals to/from the common buses 20, 30 by protocol control, each of the common interface parts 10a to 14a is provided with a primary destination ID decision circuit for deciding primary destination ID inserted into a packet transmitted through respective common buses 20, 30 by using protocol control.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to internal wiring of a large-scale semiconductor integrated circuit used in an information processing device or the like,
In particular, the present invention relates to a bus wiring for interblock connection in a large-scale semiconductor integrated circuit having a plurality of functional blocks.

[0002]

2. Description of the Related Art There are various types of semiconductor integrated circuits used in electronic devices such as information processing devices and communication devices, but system LSIs (large-scale integrated circuits) generally use MPs.
In addition to the control unit (control unit) consisting of U etc.,
Various processing units for executing various data processing and the like, and a storage unit (memory unit) are provided. The memory unit may be directly controlled by the control unit or indirectly controlled by a memory unit controller dedicated to the memory unit.

By the way, since recent control units such as MPUs have become faster, there is a demand for faster data transfer to and from the memory unit. As a memory unit that speeds up data transfer with the control unit, for example,
A memory unit of a protocol control system such as a RAMBUS specification is known. A protocol control type memory unit can easily connect to a standardized bus by protocol control regardless of the capacity of the memory unit, and can transfer data at high speed.

FIG. 17 is a block diagram showing a structure of a main part of a conventional system LSI having a protocol control type memory unit.

The conventional system LSI shown in FIG.
A control unit 1 such as an MPU, a first processing unit 2 that executes an arbitrary first process, a second processing unit 3 that executes a second process,
It has an nth processing unit 4 for executing the nth processing, a storage unit 5 of a protocol control system, and a clock generation unit 8 for generating a reference signal (clock signal) and outputting it from a clock signal line 40. .

In the control unit 1, an interface (I / O) unit 2b dedicated to the first processing unit 2, an interface (I / O) unit 3b dedicated to the second processing unit 3, and an interface dedicated to the nth processing unit 4 are provided. (I / O) unit 4b, interface (I / O) unit 5b dedicated to the storage unit 5, interface (I / O) unit 6b dedicated to the (n-m) th processing unit, and input / output at each interface unit. It has a timing adjusting section 7 for adjusting the timing of the signal to be read. Further, the I / O unit 5b in this case has a function as a memory unit controller.

On the other hand, a dedicated interface (I / O) section 2a is also provided in the first processing section 2. Similarly, a dedicated interface (I / I) is provided in the second processing unit 3.
A dedicated interface (I / O) unit 4a is provided in the O) unit 3a and the nth processing unit 4, and a dedicated interface (I / O) unit 5a is provided in the storage unit 5.

The I / O unit 2b dedicated to the first processing unit 2 in the control unit 1 and the dedicated I / O unit 2a in the first processing unit 2 are composed of a plurality of dedicated signal lines. The first processing unit dedicated bus 2c is connected.

Similarly, the I / O unit 2b dedicated to the second processing unit 3 and the dedicated I / O unit 3a in the second processing unit 3 are the second processing units each composed of a plurality of dedicated signal lines. Partial bus 3c
The I / O unit 4b dedicated to the nth processing unit 4 and the dedicated I / O unit 4a in the nth processing unit 4 are connected to each other by an nth processing unit dedicated bus composed of a plurality of dedicated signal lines. 4c, and the dedicated I / O unit 5b in the storage unit 5 and the dedicated I / O unit 5a in the storage unit 5 are connected by a dedicated storage unit bus 5c composed of a plurality of dedicated signal lines. There is.

Further, an I / O unit 6b dedicated to the (n-m) th processing unit in the control unit 1 and a dedicated interface (I / O) unit not shown in the (n-m) th processing unit The two are also connected by a dedicated bus 6c for the (n-m) th processing unit, which is composed of a plurality of dedicated signal lines.

In this system LSI, for example, the storage unit 5
Read the stored data from the
The operation for outputting to the outside of I is executed as follows.

(1) The read command generated by the control unit 1 is encoded by the memory unit controller in the I / O unit 5b and then packetized to the I / O unit 5a in the storage unit 5. Sent out.

(2) In the storage unit 5, the stored data is read based on the received read command,
It is packetized by the I / O unit 5a and sent to the I / O unit 5b.

(3) The memory unit controller of the I / O unit 5b decodes the received data, adjusts the timing as necessary, and then transmits the data to the processing unit designated by the control unit 1 via a dedicated bus. To transfer the data. Hereinafter, for example, the first processing unit 2 is an external output interface.

(4) Before the data is transferred from the control unit 1 to the first processing unit 2 via the dedicated bus 2c, or simultaneously with the data transfer, the dedicated bus 2c is transferred from the control unit 1 to the first processing unit 2. A command regarding the output method is sent via.

(5) The first processing unit 2, which has received the command and the data, outputs the received data to the outside of the system LSI.

As described above, inside the conventional system LSI, for example, when reading data from the memory unit, dedicated I / O units provided in the control unit 1 and each processing unit / storage unit are provided. In addition, commands and data are transmitted and received via a dedicated bus composed of a plurality of signal lines.

[0018]

However, in the configuration of the conventional system LSI, as described above, an individual bus for each processing unit consisting of a dedicated line is provided between the control unit 1 and each processing unit / storage unit. Since they are connected with each other, there is a problem that the number of wirings is large and it takes a long time to connect the wirings.

Further, since the buses are individual, the signal input / output systems between the control unit 1 and each processing unit / storage unit are also different, so that the signals are output to each processing unit / storage unit. Timings of signals or signals input from each processing unit / storage unit are individually different. Therefore, the control unit 1 needs to be provided with the signal timing adjusting unit 7 for exchanging signals and data with each processing unit / storage unit. In order to reduce the processing load of the control unit, when the signal timing is adjusted without using the timing adjustment unit 7 described above, for example, the delay for each wiring between the control unit 1 and each processing unit / storage unit is adjusted. In order to achieve this, design changes such as changing / adjusting the arrangement of each unit, adding a signal or data repeater circuit, changing the I / O unit and driver unit in the control unit 1 and each processing unit / storage unit, etc. It is necessary and there is a problem that the design time increases.

Further, for example, when data is read from the storage unit and output to the outside of the system LSI, the data read from the storage unit is first transferred via a dedicated bus between the storage unit and the control unit. Since it is sent to the control unit once and then transferred from the control unit to the processing unit of the external interface via the dedicated bus for the processing unit, a long access time is required and the control unit also controls the data transfer. Therefore, there is a problem that the processing load of the control unit is large.

The present invention has been made in order to solve the above-mentioned conventional problems, and reduces the number of wirings and the access time without increasing the design time or the processing load of the MPU. It is an object of the present invention to provide a large-scale semiconductor integrated circuit such as a system LSI that reduces the power consumption.

[0022]

In order to achieve the above-mentioned object, a semiconductor integrated circuit according to a first aspect of the present invention connects a control unit and a plurality of other functional units, and transmits signals of each unit. And a common interface unit that is provided in each of the control unit and the plurality of other functional units and performs signal transfer to and from the common bus by protocol control. The common interface unit is an internal circuit of the input system. And a primary destination ID determination circuit for determining the primary destination ID inserted in the packet transmitted using protocol control via each of the common buses.

According to a second aspect of the present invention, in the semiconductor integrated circuit according to the first aspect, the common bus includes a common first bus for transmitting a downward signal from the control section to each functional section, and each common bus. It is characterized in that there are two systems of the common second bus for transmitting signals in the upstream direction from the function unit to the control unit.

According to a third aspect of the present invention, in the semiconductor integrated circuit according to the second aspect, the common first bus and the common second bus are provided.
Each bus has a dedicated clock generator.

According to a fourth aspect of the present invention, in the semiconductor integrated circuit according to the third aspect, each packet transmitted through each common bus has the first cycle of the packet at the beginning of the packet. Are included in the packet start control bit.

According to a fifth aspect of the present invention, in the semiconductor integrated circuit according to the fourth aspect, the common interface section includes a packet start control bit in the input system circuit and a clock signal from the clock generation section. It is characterized by having an AND circuit which outputs at an input timing.

According to a sixth aspect of the present invention, in the semiconductor integrated circuit according to the fourth or fifth aspect, each packet transmitted through each common bus has a packet start control bit after the packet start control bit. It is characterized by having a primary destination ID bit which indicates where the packet is to be processed.

According to a seventh aspect of the present invention, in the semiconductor integrated circuit according to the sixth aspect, the common interface section determines a primary destination ID bit in the input system circuit. It is characterized by having.

The present invention according to claim 8 is the semiconductor integrated circuit according to claim 6 or 7, wherein each packet transmitted via each common bus is a primary destination I of the packet.
It is characterized by having a secondary destination ID bit for transferring the processing result of the functional unit designated by the primary destination ID bit after the D bit.

According to a ninth aspect of the present invention, in the semiconductor integrated circuit according to the eighth aspect, the common interface section includes a secondary destination ID register for storing a primary destination ID bit in the input system circuit. The output destination circuit has an output secondary destination ID register to which the secondary destination ID stored in the input destination secondary destination ID register is transferred.

According to a tenth aspect of the present invention, in the semiconductor integrated circuit according to the eighth or ninth aspect, the common interface section uses the primary destination ID to execute the processing first based on each packet. And a destination of the processing result in the functional unit designated by the primary destination ID is selected by the secondary destination ID.

The present invention according to claim 11 relates to claim 4,
In the semiconductor integrated circuit according to 6 or 8, each packet transmitted via each common bus has:
It is characterized by having a power save bit for putting the semiconductor integrated circuit into a power save state.

The present invention according to claim 12 provides the invention according to claim 11.
In the semiconductor integrated circuit described in the paragraph 1, the common interface section has a power save determination circuit for determining a power save bit in the input system circuit.

According to a thirteenth aspect of the present invention, in the semiconductor integrated circuit according to the eighth aspect, each packet transmitted via each common bus has a secondary destination ID in the packet.
It is characterized by having a command bit for storing a command for the functional unit designated by.

The present invention of claim 14 is the same as that of claim 13.
In the semiconductor integrated circuit described in the paragraph 1, the common interface section has a first register for storing a command bit in the input system circuit, and the secondary destination I in the output system circuit.
It is characterized in that it has a second register for transferring a command bit to the functional unit designated by D, and the stored contents of the first register are transferred to the second register.

According to a fifteenth aspect of the present invention, in the semiconductor integrated circuit according to the eighth aspect, each packet transmitted via each common bus is a data / command for storing the data or command in the packet. Bit length,
The variable length is optimized by optimizing the processing contents executed by the functional unit designated by the primary destination ID.

The present invention of claim 16 provides the invention of claim 15
In the semiconductor integrated circuit according to [1], the common interface unit is an output system circuit, and the secondary destination ID is added to the packet output to the functional unit designated by the primary destination ID.
It is characterized in that packets to be output to the functional unit designated by are continuously output.

The present invention according to claim 17 provides the invention according to claim 4,
In the semiconductor integrated circuit according to 6 or 8, each packet transmitted via each common bus has:
It is characterized by having a data output pattern bit indicating whether data output from the functional unit designated by the primary destination ID is continuously executed or intermittently executed.

The present invention of claim 18 is the same as that of claim 17
In the semiconductor integrated circuit described in the above item 1, the common interface section has an output pattern determination circuit for determining a data output pattern bit in the input system circuit.

[0040]

BEST MODE FOR CARRYING OUT THE INVENTION The present invention will be described below based on the illustrated embodiments. Embodiment 1. FIG. 1 is a diagram showing a configuration of a system LSI device according to a first embodiment of the present invention.

In FIG. 1, parts having the same functions as those of the conventional system LSI device shown in FIG. 17 are designated by the same reference numerals, and duplicated description will be omitted.

In the present embodiment shown in FIG. 1, the control unit 1
0, the first processing unit 11 and the second processing unit 1 which are other functional units
2, the nth processing unit 13, and the storage unit 14 are connected to each other by a common data bus. The common data bus is a bus composed of a plurality of wires such as 17 lines, and in the present embodiment, a direction from the control unit 10 to other functional units (hereinafter, referred to as a down direction for convenience). And a second system in the direction from the other functional unit to the control unit (hereinafter, referred to as an up direction for convenience). In FIG. 1, the downstream first system is the common first bus 20, and the upstream second system is the common second bus 20.
It is the bus 30. The up direction or the down direction in this embodiment is a direction for convenience of facilitating the description of this embodiment, and can be replaced with any other direction.

Further, the control unit 10, the first processing unit 11, the second processing unit 12, the nth processing unit 13 of the present embodiment, and
In the storage unit 14, the common first bus 20 or the common second bus 20 is used.
A common-specification interface for exchanging signals with the bus 30 using a protocol control method is mounted in each unit. The interface of the control unit 10 is the common I / O 10a, and similarly, the interface of the first processing unit 11 is the common I / O 11a, the interface of the second processing unit 12 is the common I / O 12a, and the interface of the nth processing unit 13. Is the common I / O 13a, and the interface of the storage unit 14 is the common I / O 14a.

The reference signal (clock signal) for the common first bus 20 is generated by the clock generator 8a and output as the clock signal CK1 from the clock signal line 40a, and the reference signal (clock signal) for the common second bus 30 is generated. Is generated by the clock generator 8b and output as the clock signal CK2 from the clock signal line 40b.

Further, "111110" is assigned as an address to the control unit 10 of the present embodiment, "111101" is assigned as the address of the first processing unit 11, "111100" is assigned as the address of the second processing unit 12, and The address of the nth processing unit 13 is “111000”, and
“110111” is assigned as the address of the storage unit 14. Further, "000000" is assigned as an address when all parts are designated, and "111111" is assigned as an address when all parts are not designated.

FIG. 2 is a diagram showing a protocol (packet structure) used in the common first bus 20 shown in FIG.

The row in the horizontal direction shows the numbers (0 to 16) of each of the 17 common bus lines, and the row in the vertical direction shows the number of cycles. In the present embodiment, since one packet has 9 cycles, the cycle numbers 0 to 8 are shown in the column.

Among the signals of one packet of the common first bus 20, in the 0th cycle, one bit of the bus line number 16 is used as a packet start control bit A indicating the start of each packet.
-1, 6 bits of bus line numbers 15 to 10 are primary destination ID bits B-1 and 6 bits of bus line numbers 9 to 4 are secondary destination ID bits D-1. In the first to eighth cycles, 16 bits of bus line numbers 15 to 0 are set as data / command bit C-1.

4 of the 0th cycle bus line numbers 3 to 0
The bit and each 1 bit of the bus line number 16 in the first to eighth cycles (8 bits in total) are not used in the downstream direction of the present embodiment.

FIG. 3 is a diagram showing a protocol (packet structure) used in the common second bus 30 shown in FIG.

The column in the horizontal direction indicates the number (0 to 16) of each of the 17 common bus lines, the column in the vertical direction indicates the number of cycles, and one packet is 9 cycles. Is similar to FIG. 2 in that the cycle numbers 0 to 8 are shown.

Among the signals of one packet of the common second bus 30, in the 0th cycle, one bit of the bus line number 16 is a packet start control bit A indicating the start of each packet.
-2, 6 bits of bus line numbers 15 to 10 are designated as the primary destination ID bit B-2. In the first to eighth cycles, 16 bits of bus line numbers 15 to 0 are set as data / command bit C-2.

1 of bus line number 9 to 0 in the 0th cycle
The 0 bit and each 1 bit of the bus line number 16 in the first to eighth cycles (8 bits in total) are not used in the upstream direction of the present embodiment.

Each bit shown in FIGS. 2 and 3 is connected to the common I / O of each section from the GTL (Gunning T).
It is output in the format of (Transceiver Logic).

FIG. 4 shows common I / Os 11a, 12a, 13a built in the control unit 10 of FIG. 1 or other functional units.
FIG. 14 is a block diagram showing an internal configuration of 14a. In the common I / O 10a of the control unit 10, the output side is connected to the common first bus 20, and the common second bus 30 is connected.
Since the input side is connected to the input side, the upstream and downstream sides are connected in reverse to the configuration shown in FIG. 4, but the common I / O configuration is common I / O in other functional units. It is the same.

The common I / O shown in FIG. 4 is roughly divided into an input system 50 for performing an interface process for an input from the common first bus 20 or the common second bus 30, and a common first bus 20 or the common second bus. The output system 60 is configured to perform interface processing for the output to the bus 30.

The input system 50 has the following circuit configuration.

(A) The bus input buffer 5 to which all the input signals from the 17 bus lines of the common first bus 20 and the clock signal CK1 from the clock signal line 40a are input
1.

(B) An input counter 52 to which the bus line number 16 input signal, the clock signal CK1 from the clock signal line 40a, and a signal output from a primary destination ID determination circuit 54 described later are input.

(C) An AND circuit 53 to which the bus line number 16 input signal and the output signal from the input counter 52 designating 0 cycle are input.

(D) A primary output which outputs a signal to the input counter 52 when the input signals of the bus line numbers 10 to 15 and the output signal of the AND circuit 53 are input and the primary destination ID matches the stored content. Destination ID determination circuit 54.

(E) Secondary destination I which is the output destination for outputting the processing result in the functional unit designated by the primary destination ID.
Secondary destination I for temporarily storing D and transferring it to the output system 60
D register 55.

(F) Bus line numbers 10 to 15 input signals and an output signal from the input counter 52 designating any one of 1 to 4 cycles are input, and the cycle of the cycle designated by the output of the input counter 52 is input. A 1- to 4-cycle register 56a for temporarily storing an input signal.

(G) The bus line number 10 to 15 input signal and the output signal from the input counter 52 designating any one of 5 to 8 cycles are input, and the cycle of the cycle designated by the output of the input counter 52 is input. 5 to 8 cycle register 56b for temporarily storing the input signal.

(H) 1-4 cycle registers 56a and 5
An internal output buffer 57 that temporarily stores the output of the 8-cycle register 56b for input to an internal circuit.

Further, the output system 60 has the following circuit configuration.

(I) An internal input buffer 67 for temporarily storing the output from the internal circuit and outputting it to the 1 to 4 cycle register 66a and the 5 to 8 cycle register 66b.

(M) The bus line number 10 to 15 output signal and the output signal from the output counter 62 designating any one of the 1 to 4 cycles are input, and the cycle of the cycle designated by the output of the output counter 62 is input. A 1 to 4 cycle register 66a for temporarily storing an input signal.

(N) The bus line number 10 to 15 output signal and the output signal from the output counter 62 designating any one of 5 to 8 cycles are input, and the cycle of the cycle designated by the output of the output counter 62 is input. 5 to 8 cycle register 66b for temporarily storing an input signal.

(K) When an output signal designating 0 cycles of the output counter 62 is input, the secondary destination ID register 5
The secondary destination ID transferred from 5 is the bus line number 10
Secondary destination ID register 6 that outputs an output signal to
5.

(L) An output counter 62 which outputs a cycle number of 0 to 8 when the clock signal CK2 from the clock signal line 40b is input.

(M) When the clock signal CK2 from the clock signal line 40b is input, 17 of the common second bus 30 is input.
A bus output buffer 61 that outputs all output signals to the bus line of the book.

Although simplified in FIG. 4, the bus input buffer 51, the bus output buffers 61, 2 are shown.
The next-destination ID register 55 and the secondary-destination ID register 65 are composed of 17 or 6 individual registers for each common bus line. In addition, the 1 to 4 cycle register 56a, the 1 to 4 cycle register 66a,
The 5-8 cycle register 56b and the 5-8 cycle register 66b are composed of 64 individual registers for each common bus line and for each cycle.

Further, each register is connected to each corresponding common bus line and each corresponding counter.

FIG. 5 is a chart showing the timing of a packet signal composed of a pulse signal of 9 cycles used in this embodiment, and when the second processing section 12 is an output interface to an external circuit, it is a control section. 10 reads data from the storage unit 14 (for common first bus:
1 bus request) 1st packet request, 2nd processing unit 1
This is a case where the data read from 2 is output to an external circuit.

FIG. 5A shows the clock generator 8 periodically.
Generated by the clock signal line 40a /
It is the clock signal CK1 / 2 supplied from b. Figure 5
(B) shows the timing of each packet signal transmitted on the common first bus 20. FIG. 5C shows the common second bus 3
0 shows the timing of each packet signal transmitted.

In the case of FIG. 5B, the packet start control bit (1 bit) indicating the start of the first packet (for 1 bus) becomes "0" and the primary destination ID bit (6 bits).
Becomes “110111” indicating the storage unit 14, and the secondary destination bit (6 bits) indicates “1111” indicating the second processing unit 12.
00 ”, and the data / command bit (16 × 8 cycles = 138 bits) includes“ command and ROW address for read operation ”,“ plurality of column addresses ”,
The "specified bit of the data mask" is included.

First, as shown in FIG. 5B, when the first packet (for one bus) is transmitted on the common first bus 20,
Each unit (first processing unit 11 to 11) connected to the common first bus 20
In the storage unit 14), the bus input buffer 51, the input counter 52, the AND circuit 53, and the primary destination ID determination circuit 54 are used to determine whether the packet start control bit is "0". It When the packet start control bit is "0", both the "0" output of the input counter 52 and the bus line number 16 of the bus input buffer 51 become high (H), and the AND circuit 53 outputs a signal. It In the primary destination ID determination circuit 54 which receives the signal from the AND circuit 53, the ID stored in advance and the bus line 10 are stored.
It is determined whether or not the own processing unit is designated by comparing with the IDs input from 15 to 15, and a signal is output to the input counter 52. In this case, “110111” indicating the storage unit 14
Is determined.

When the judgment result of the input ID and the previously stored ID are in agreement, the input counter 52 is incremented by 1 and the second cycle of the packet signal taken in the bus input buffer 51 is registered in the 1 to 4 cycle register. Take in 56a. Thus, each time the input counter 52 advances,
The packet signal is sequentially captured in the third and fourth cycles, and finally up to the ninth cycle. Thereafter, the signal is transferred to the internal output buffer 57, and the signal converted so as to be suitable for the internal circuit is sent out to the internal circuit. In addition, the input ID and the previously stored I
If the determination results of D do not match, the input counter 52 does not advance, so the packet signal is not captured.

"11011" of the first packet (for 1 bus)
Since "1" is an ID indicating the storage unit 14, even if the packet signal obtained from the common first bus 20 is fetched in each unit and the above processing is performed, the input ID and the I stored in advance are stored.
Only in the storage unit 14, the determination results of D match.
In the subsequent process, the read process of the data stored only in the storage unit 14 is performed.

Similarly, the secondary destination ID register 55 receiving the signal from the AND circuit 53 stores the signal (secondary destination ID) input from the bus lines 4 to 9 and then outputs the signal to the output system 6.
The secondary destination ID of 0 is transferred to the secondary destination ID register 65.

The second packet (for one bus) shown in FIG. 5B is a packet for instructing the second processing unit 12 starting from the 10th cycle after the end of the first packet.
The packet start control bit (1 bit) indicating the start of the second packet (for 1 bus) is "0", and the primary destination ID
Bits (6 bits) indicate “1111” indicating the second processing unit 12.
00 ”, the secondary destination bit (6 bits) is“ 111111 ”indicating an unspecified address, and the data / command bit (16 × 8 cycles = 138 bits) includes“ Data from storage unit 14 to external circuit ”. Command to output ”is included.

The second packet (for 1 bus) is transmitted to the respective processing units 11 to 13 and the storage unit 14 via the common first bus 20, and is connected to the common first bus 20 (first processing unit). 11 to storage unit 14), as in the case of the first packet (for 1 bus), it is determined whether the packet start control bit is "0", the signal output from the AND circuit 53, the primary output I stored in advance in the destination ID determination circuit 54
A comparison judgment between D and the input ID and a signal to the input counter 52 are output. In this case, “111100” indicating the second processing unit 12 is determined.

Further, thereafter, similarly to the case of the first packet (for one bus), the input ID and the I stored in advance are stored.
When the determination result of D is a match, the input counter 52 is incremented by 1, and the 2nd to 9th cycles of the packet signal fetched in the bus input buffer 51 are the 1st to 4th cycle registers 5
The signal which is fetched by the 6a and the 5-8 cycle register 56a, transferred to the internal output buffer 57, and converted from there to be adapted to the internal circuit is sent out to the internal circuit. In addition, the input ID and the previously stored I
If the D determination results do not match, the packet signal is not captured. The second processing unit 12, which has received this packet, waits for data input by the command in the packet.

The first packet shown in FIG. 5C (for common second bus: hereinafter, described as two buses) is a packet output from the storage unit 14 that has received the first packet (for one bus). Is. The storage unit 14 outputs the output system 60 at the 19th cycle from the signal end timing of the first packet (for 1 bus).
Of the output counter 62 of 1 to 4 is sequentially incremented from "0" to 1 to 4 cycle register 66a, and
The contents of the 5 to 8 cycle register 66b are output as the first packet (for 2 buses). When the output of the output counter 62 is “0”, the packet start control bit is set to “0” and the secondary destination ID register 65 outputs “111100” indicating the second processing unit 12, and the output counter 6
When the output of 2 is "1 to 8", the read output data output from the storage unit 14 is output to the common second bus 30 as a data / command bit.

Upon receiving the first packet (for two buses) from the common second bus 30, the second processing unit 12 receives the second packet (for one bus).
Since the data input wait state is instructed by the packet, the read output data is fetched from the common second bus 30 to start the processing.

FIG. 6 is also a chart showing the timing of a packet signal consisting of a 9-cycle pulse signal used in this embodiment. For example, when the first processing section 11 is an input interface from an external circuit, This is a case where the data is fetched from the external circuit to the first processing unit 11 and the fetched data is stored in the storage unit 14.

Similar to FIG. 5, FIG. 6A shows a clock signal which is periodically generated by the clock generator 8 and supplied from the clock signal line 40 as a reference signal. Figure 6
(B) shows the timing of each packet signal transmitted on the common first bus 20. FIG. 6C shows the common second bus 3
0 shows the timing of each packet signal transmitted.

In the case of FIG. 6B, the packet start control bit (1 bit) indicating the start of the first packet (for 1 bus) becomes "0" and the primary destination ID bit (6 bits).
Becomes “111101” indicating the first processing unit 11, and the secondary destination bit (6 bits) indicates “1101” indicating the storage unit 14.
11 ”, and the data / command bit (16 × 8 cycles = 138 bits) includes“ data taken in from the outside ”and“ bit outputting the taken data to the common first bus 20 ”.

First, as shown in FIG. 6B, when the first packet (for one bus) is transmitted from the control unit 10 via the common first bus 20, each unit (first unit) connected to the common first bus 20 1 processing unit 11 to storage unit 14), the bus input buffer 5
1, the input counter 52, the AND circuit 53, and the primary destination ID determination circuit 54 are used to determine whether or not the packet start control bit is "0". If the packet start control bit is “0”, the input counter 5
Both the “0” output of 2 and the bus line number 16 of the bus input buffer 51 become high (H), and a signal is output from the AND circuit 53. Upon receiving the signal from the AND circuit 53, the primary destination ID determination circuit 54 compares the stored ID with the ID input from the bus lines 10 to 15 to determine whether or not the own processing unit is designated, and input. A signal is output to the counter 52. In this case, “111101” indicating the first processing unit 11 is determined.

Next, the second packet (for one bus) is transmitted from the first processing unit 11 on the common first bus 20 following the first packet (for one bus).

In the second packet (for 1 bus), the packet start control bit (1 bit) indicating the start of the second packet (for 1 bus) becomes "0", and the primary destination ID bit (6 bits) is stored. The part 14 is "110111", the secondary destination bit (6 bits) is "111111" indicating an unspecified address, and the data / command bit (16 × 8 cycles = 138 bits) is "data write command and ROW". Address ”,“ plurality of column addresses ”, and“ specified bit of data mask ”are included.

In the second packet (for one bus) shown in FIG. 6B, the primary destination ID bit indicates “11” in the storage unit 14.
Since it is “0111”, the write operation is started by the “write command and ROW address” and the “column address”, and the data input waiting state is set.

The third packet (for one bus) shown in FIG. 6B is the first processing unit 1 based on the first packet (for one bus).
1 is a packet for outputting the data taken in. At the 10th cycle after the completion of the first packet (for 1 bus), the up counter circuit 62 counts up from "0" to "8" in order, and the 1st to 4th cycle register 66a and the 5th to 8th cycle register The contents of 66b are output. The output of the output counter 62 is "0".
In this case, the packet start control bit is set to “0” and 1
Next destination ID bit is “110111” indicating the storage unit 14.
That is, the data taken into the first processing unit 11 is output to the common first bus 20 as a data / command bit.
The fourth packet (for 1 bus) is also a packet for outputting the data taken in by the first processing unit 11, like the third packet (for 1 bus), and the primary destination ID bit is the storage unit 14 “110111” indicating that the data is captured by the first processing unit 11 and is output to the common first bus 20 as a data / command bit.

Further, in this case, packet transmission is not carried out on the upstream bus 30 shown in FIG. 6 (c).

As described above, in the present embodiment, the control unit,
Also, specify a dedicated address (ID) for each processing unit,
By setting the protocol and designating the primary destination ID, the control unit and a plurality of different processing units can be connected to a common bus. Further, by specifying the secondary destination ID in addition to the primary destination ID, for example, the data stored in the storage unit can be transferred to an external circuit without going through the control unit, and conversely, input from the external circuit. The signal or data generated by each processing unit is stored in the storage unit without passing through the control unit, or the processing result of the processing unit designated by the primary destination ID is transferred to the secondary processing unit without passing through the control unit. It becomes possible to directly transfer to the destination ID.

Further, a common interface (I / O) for performing common protocol control is provided to the control unit, the storage unit, and the other processing units, and each unit is connected by the common first bus and the common second bus. Thus, there is no difference in signal delay due to wiring delay, and therefore it is not necessary to install a repeater for reducing wiring delay. Therefore, it is possible to simplify the wiring pattern of the correction circuit. In particular, even when the wiring pattern is conventionally required in multiple layers, in the present embodiment, it is possible to perform wiring with only the wiring pattern of the uppermost layer, which reduces the design time. be able to. Embodiment 2. In recent years, integrated circuits are required to suppress the influence on global warming or to support power save control that suppresses power consumption for reasons such as being advantageous in battery driving. In a second embodiment shown below, a case where an integrated circuit has a power saving function will be described.

FIG. 7 is a diagram showing a protocol (packet structure) used in the common first bus shown in FIG. In FIG. 7, bits required for power save control of the integrated circuit are added to the empty bits of the downstream protocol (packet configuration) of FIG. 2 of the first embodiment. A power save bit E-1 is added to 16 cycle numbers 1 to 3.

FIG. 8 shows a common I / O incorporated in each section of FIG.
It is a block diagram which shows the internal structure of O. In FIG. 8, the above-mentioned bus line number 16 is added to the configuration of FIG. 4 of the first embodiment.
By determining the power save bit E-1 of the cycle numbers 1 to 3 of the power save determination circuit 58, it is possible to determine whether or not the power save state is set.
0 has been added.

The power save determination circuit 58 receives the input signal of the bus line number 16 and the input counter 52 from 1 to 3
The cycle count value is input, and the determination result of the power save state is output to the input counter 52 and the output counter 62 to which the clock signal is input, and the internal circuit of the integrated circuit.

The operation of the second embodiment differs from the operation of the first embodiment described with reference to FIGS. 1 to 6 in that the power save operation can be performed. There are two types of power save operations. One is power down, which makes all the circuits have the least standby current.
The other is a standby in which the standby current of the circuit excluding the interface section is the smallest.

First, the case of power down will be described. The packet start control bit (1 bit) indicating the beginning of the first packet (for 1 bus) becomes “0”, and the primary destination ID bit (6 bits) indicates all processing units, control units, storage units, etc. It becomes "000000" to be specified, and the power save bit E-1 has "0", 2 in the first cycle.
“1” is input in the third cycle and the third cycle, and the power save command becomes “011”. The secondary destination bit (6 bits) is "111111" indicating no designation,
“1” is input to the data / command bit (16 × 8 cycles = 138 bits).

(For 1 bus) Since the packet start control bit (1 bit) indicating the beginning of the first packet is "0", the primary destination ID bit (6 bits) is fetched and the count of the input counter 52 is counted. Up is started.

The power save commands from the first cycle to the third cycle are fetched by the power save determination circuit 58. Here, the power save command is "011".
Therefore, the power save determination circuit 58 determines that the power is down, outputs a power down command to the internal circuit, stops the counter output from the output counter 62, and the input counter 52 also outputs the packet start control bit. All the circuits are put into the power-down state by stopping outputs other than the counter output required for fetching.

Next, the case of standby will be described. The packet start control bit (1 bit) indicating the beginning of the first packet (for 1 bus) becomes “0”, and the primary destination ID bit (6 bits) indicates all processing units, control units, storage units, etc. The designated power is "000000", "0" is input to the power save bit E-1 in the first and second cycles, and "1" is input in the third cycle, and the power save command is "001". The secondary destination bit (6 bits) is "111111" indicating no designation,
“1” is input to the data / command bit (16 × 8 cycles = 138 bits).

(For 1 bus) Since the packet start control bit (1 bit) indicating the start of the first packet is "0", the primary destination ID bit (6 bits) is taken in and the count of the input counter 52 is counted. Up is started.

The power save commands from the first cycle to the third cycle are fetched by the power save determination circuit 58. Here, the power save command is "001"
Therefore, the power save determination circuit 58 determines the standby state and outputs the standby command to the internal circuit to put the internal circuit in the standby state. In this case, the output of the output counter 62 and the input counter 52 is not stopped.

Next, the case of returning from the power save mode such as power down or standby will be described. The packet start control bit (1 bit) indicating the start of the first packet (for 1 bus) becomes "0", and the primary destination ID bit (6 bits) indicates "11111".
1 "," 0 "is input to the power save bit E-1 in all the first to third cycles, and the power save command becomes" 000 ". The secondary destination bit (6 bits) is "111111" indicating no designation,
“1” is input to the data / command bit (16 × 8 cycles = 138 bits).

(For 1 bus) Since the packet start control bit (1 bit) indicating the start of the first packet is "0", the primary destination ID bit (6 bits) is fetched and the count of the input counter 52 is counted. Up is started.

The power save commands from the first cycle to the third cycle are fetched by the power save determination circuit 58. Here, the power save command is "000"
Therefore, the power save determination circuit 58 determines to return from the power save mode, and outputs a power down or standby return command to the internal circuit to restore the internal circuit. In addition, the output that has been stopped by the output counter 62 or the input counter 52 at the time of power down is also restored (enabled).
Let

As described above, according to the second embodiment, in addition to the effects of the first embodiment, the entire integrated circuit can be simultaneously shifted to the power save state and the power consumption can be reduced. Further, since the circuit to be shifted to the power save state can be designated by the primary destination ID bit, only the arbitrary circuit can be brought into the power save state. Further, since 3 bits are used as the power save command, it is possible to select and execute the power down state in which power is saved for the entire integrated circuit and the standby state in which power is saved except for the interface section.

In the above-described second embodiment, the case where the number of power save bits E-1 is 3 has been described, but the present invention is not limited to this.
As the bit number of the power save bit E-1, another arbitrary number such as 5 bits or 8 bits may be used. Embodiment 3. In the above-described first embodiment, the processing load of the control unit can be reduced by not controlling the data transfer by the control unit. For example, the second packet (for one bus) in FIG. Regarding the command for the secondary destination ID, it was output from the control unit as another packet. If the command for this secondary destination ID can be put in the data / command bit of 2 to 9 cycles of the first packet (for 1 bus) and output, for example, the second packet (for 1 bus) is unnecessary. Therefore, the processing load on the control unit can be further reduced.
In the third embodiment described below, a case will be described in which a command for a secondary destination ID is put in data / command bits and output.

FIG. 9 is a diagram showing a protocol (packet structure) used in the common first bus shown in FIG. In FIG. 9, the data / command bit C-1 of the downstream protocol (packet structure) of FIG. 2 of the first embodiment is halved to cycle numbers 1 to 4, and instead of that,
2 for cycle numbers 5-8 of bus line numbers 0-15
A command bit G-1 for the next destination ID is inserted.

FIG. 10 is a diagram showing a protocol (packet structure) used in the common second bus shown in FIG.
In FIG. 10, the data / command bit C-2 of the upstream protocol (packet configuration) of FIG. 3 of the first embodiment is halved to cycle numbers 5 to 8, and instead, bus line numbers 0 to A command bit G-2 for the secondary destination ID is inserted in the cycle numbers 1 to 4 of 15.

FIG. 11 shows a common I built in each part of FIG.
It is a block diagram which shows the internal structure of / O. In FIG.
The output of the 5 to 8 cycle register 56b (first register) located on the input side 50 in the configuration of the first embodiment is not input to the internal buffer 57, and the 1 to 4 cycle register 66a on the output side 60. It is connected so as to be input to the (second register). Also, the output from the internal buffer 67 on the output side 60 is the 1 to 4 cycle register 6
6a (second register) is not input.

The operation of the third embodiment differs from the operation of the first embodiment described with reference to FIGS. 1 to 6 in that the control section 10 outputs the common first bus 20 of FIG. 5 (1 Even if there is no second packet (for bus), data can be output from the second processing unit 12 to the external circuit only by the first packet (for two buses) output from the storage unit 14.

The operation of the first packet (for one bus) is similar to that of the first embodiment, but as shown in FIG. 9, the bus line numbers 0 to 15 and the cycle numbers 5 to 8 are used.
, The command bit G-1 for the secondary destination ID is inserted. This includes a command for the second processing unit 12 to output the data received from the storage unit 14 to an external circuit. Further, as described above, the second packet (for 1 bus) of FIG. 5B of the first embodiment is not output from the control unit in the present embodiment.

The second packet (for one bus) is transmitted to the processing units 11 to 13 and the storage unit 14 via the common first bus 20, and is connected to the common first bus 20 (first processing unit). 11 to storage unit 14), as in the case of the first packet (for 1 bus), it is determined whether the packet start control bit is "0", the signal output from the AND circuit 53, the primary output I stored in advance in the destination ID determination circuit 54
A comparison judgment between D and the input ID and a signal to the input counter 52 are output. In this case, “111100” indicating the second processing unit 12 is determined.

Further, thereafter, similarly to the case of the first packet (for one bus), the input ID and the I stored in advance are stored.
When the determination result of D is a match, the input counter 52 is incremented by 1, and the 2nd to 9th cycles of the packet signal fetched in the bus input buffer 51 are the 1st to 4th cycle registers 5
The signal which is fetched by the 6a and the 5-8 cycle register 56a, transferred to the internal output buffer 57, and converted from there to be adapted to the internal circuit is sent out to the internal circuit. In addition, the input ID and the previously stored I
If the D determination results do not match, the packet signal is not captured. The second processing unit 12, which has received this packet, waits for data input by the command in the packet.

Also in this embodiment, FIG. 5 of the first embodiment is used.
The first packet (for 2 buses) shown in (c) is stored in the storage unit 1.
It is output from 4. In the storage unit 14, the first (for one bus)
At the 19th cycle from the signal end timing of the packet, the output counter 62 of the output system 60 is sequentially incremented from "0" to "8", and the command stored in the 1 to 4 cycle register 66a (the second processing unit 12, The command for outputting the data received from the storage unit 14 to the external circuit) and the content of the data stored in the 5 to 8 cycle register 66b are output as the first packet (for 2 buses). When the output of the output counter 62 is “0”, the packet start control bit is set to “0” and the secondary destination I
“11110” indicating the second processing unit 12 from the D register 65
0 "and the output of the output counter 62 is" 1 to 4 ", the command stored in the 1 to 4 cycle register 66a is used as the data / command bit in the common second bus 3
When the output of the output counter 62 is “5 to 8”, the read output data output from the storage unit 14 is output to the common second bus 30 as a data / command bit.

In the second processing unit 12, which has received the first packet (for two buses) from the common second bus 30, the received data is output to the external circuit by the command stored in the 1 to 4 cycle register 66a. The data is output to the external circuit by setting the process and fetching the read output data that is subsequently input from the common second bus 30.

As described above, according to the third embodiment, in addition to the effects of the first embodiment, the data in one packet /
By inserting the command used for the secondary destination ID in the command bit, the amount of packets output from the control unit can be reduced, so that the processing load of the control unit can be further reduced. It is possible to reduce the total data transfer amount in.

In the third embodiment described above, the case where the command used in the secondary destination ID inserted in the data / command bit in one packet is 6 bits has been described, but the present invention is not limited to this. Not something that, for example,
As the command used in the secondary destination ID inserted in the data / command bit, another arbitrary number such as 4 bits or 8 bits may be used. Fourth Embodiment In the above-described first embodiment, the case where a packet having a fixed data length is used has been described, but the present invention, for example, has a length (optimized) that matches the packet length with the number of bits required for each processing unit. It can also be applied to the case of using a packet of a size. In Embodiment 4 shown below,
A case will be described in which a packet having a length matching the number of bits required for each processing unit is used.

FIG. 12 is a diagram showing a protocol (packet structure) used in the common first bus shown in FIG.
For example, the common first bus 20 of the first embodiment shown in FIG.
In FIG. 12, the downlink protocol (packet configuration) of FIG. 2 of the first embodiment is halved to cycle numbers 1 to 4 for a packet such as the second packet (for 1 bus) in FIG. This is the data / command bit C
The number of cycle numbers is reduced because the number of bits of -1 is reduced as a length corresponding to the number of bits required by the processing unit indicated by the primary destination ID.

FIG. 13 is a diagram showing a protocol (packet structure) used in the common second bus shown in FIG.
In FIG. 13, the protocol (packet structure) in the upstream direction of FIG. 3 of the first embodiment is reduced by 2 cycles by the cycle numbers 1 to 6. This is also because the number of bits of the data / command bit C-2 is reduced to a length corresponding to the number of bits required by the processing unit pointed out by the secondary destination ID, so that the number of cycle numbers is reduced. .

Further, in the present embodiment, the number of hardware components can be reduced, and the number of bits of the protocol (packet configuration) is reduced as shown in FIG. When the processing unit pointed out is the second processing unit 12, the input system 50 of the second processing unit 12
5 to 8 cycle register 56b and output system 60
The 8-cycle register 66b can be eliminated. 5
Since the ~ 8 cycle registers 56b and 66b each have 64 register circuits, a total of 128 register circuits can be eliminated. Further, in the case of FIG. 13, the processing unit pointed out by the primary destination ID is, for example, the storage unit 14, and includes the 5 to 8 cycle register 56b of the input system 50 and the 5 to 8 cycle register of the output system 60. 66b
The number of registers in each can be reduced by 32 to halve. Other configurations are similar to those of the first embodiment.

The operation of the fourth embodiment is similar to the operation of the first embodiment described with reference to FIGS. 1 to 6, but the packet length can be shortened according to the required number of bits. In the first embodiment, the first packet (for 1 bus) and the second packet (for 1 bus), which are discontinuous as shown in FIG.
Can be output from.

FIG. 14 is a block diagram of FIG. 1 used in this embodiment.
A packet signal composed of a pulse signal of 7 cycles of 3,
13 is a chart showing the timing of a packet signal made up of a 5-cycle pulse signal in FIG. 12.

FIG. 14A shows a clock signal which is periodically generated by the clock generator 8 and supplied from the clock signal line 40 as a reference signal, as in FIG. 5A.
FIG. 14B shows the timing of each packet signal transmitted on the common first bus 20, but unlike FIG. 5B,
A 7-cycle clock pulse signal is used for the first packet (for 1 bus), and a 5-cycle clock pulse signal is used for the second packet (for 1 bus). FIG. 14C shows the timing of each packet signal transmitted by the common second bus 30, but unlike FIG. 5C,
A clock pulse signal of 7 cycles is used for the first packet (for 2 buses).

As described above, in the present embodiment, the length of the packet used for the transmission of signals and data can be set to the length optimized (optimized) for the storage unit 14 and the processing units 11 to 13. Because it is possible, the common first bus 20 and the common second bus 3
It is possible to improve the bus utilization efficiency of 0 or the like, and further improve the data transfer rate using the bus as compared with the first embodiment.

Further, in the above-mentioned fourth embodiment, the number of cycles of the packet used on the common first bus is 7 cycles and 5 cycles.
Although the number of cycles of packets used in the common second bus is 7 in the cycle, the present invention is not limited to this. For example, the number of cycles of packets used in the common first bus is 3 cycles. Another arbitrary number may be used, such as when there are 5 cycles or 11 cycles, or when the number of cycles of the packet used on the common second bus is 5 cycles or 13 cycles. Embodiment 5. In recent years, the amount of data of software, contents, and the like has increased, and the storage capacity required for the processing thereof has also increased. Therefore, the storage unit 14 also has a large capacity. Therefore, for example, when reading a large amount of data from the storage unit 14, the common second bus 30 may be occupied for a certain period of time. In the fifth embodiment described below, for example, even when a large amount of data is read from the storage unit 14 and output to an external circuit, the other processing units perform the common second bus 3 operation.
A case will be described in which the data reading format (output format) from the storage unit 14 can be designated as a continuous type or an intermittent type so that 0 can be used.

FIG. 15 is a diagram showing a protocol (packet structure) used in the common first bus shown in FIG.
In FIG. 15, a bit designating a data output format is added to the empty bits of the downstream protocol (packet configuration) of FIG. 2 of the first embodiment. Specifically, the bus line numbers 1 and 0 are added. The data output pattern bit F-1 is added to the cycle number 1 of. Other configurations are the same as those in FIG.

FIG. 16 shows a common I built in each part of FIG.
It is a block diagram which shows the internal structure of / O. In FIG.
An output pattern determination circuit capable of determining the data output pattern by determining the data output pattern bit F-1 of the cycle number 1 of the bus line numbers 1 and 0 in the configuration of FIG. 4 of the first embodiment. 59 is added to the input paths of the bus lines Nos. 1 and 0 in the input system 50. Other configurations are the same as those in FIG.

The input signals of the bus line numbers 1 and 0 and the output value from the AND circuit 53 are input to the output pattern determination circuit 59, and the output pattern determination result is input to the clock signal in the output system 60. Output counter 62
Is output to.

The operation of the fifth embodiment differs from the operation of the first embodiment described with reference to FIGS. 1 to 6 in that the storage unit 1
The data output pattern indicates whether the data to be output from 4 is continuously output, is output with an interval of 8 cycles based on the clock signal, or is output with an interval of 16 cycles. This is a point that can be selected by designating the bit F-1 by the control unit 10.
By this selection, for example, even when a large amount of data is being read, the processing results of other processing units are shared by the common second bus 30.
Can be notified to the control unit 10. Mutual availability of the common bus line can be improved.

First, the case where the data to be output from the storage unit 14 is continuously output will be described.

Data output pattern bit F-1 in FIG.
Is “11”, the output pattern determination circuit 59 in the common I / O 14a shown in FIG.
The "11" is detected, and the output counter 62 is notified of the continuous output.

Then, in the output system 60 in the common I / O 14a shown in FIG. 16 in the storage unit 14, as shown in FIG.
As shown in (c), when 19 cycles have elapsed after the reception of the first packet (for 1 bus) received from the common first bus 20, the first packet (for 2 buses) (output data from the storage unit) Is output to the common second bus 30. Here, since the continuous output is selected, the next upstream second
~ The n-th packet (output data from the storage unit: not shown) is output from the storage unit 14 to the common second bus 30.

Next, a case will be described in which the data to be output from the storage section 14 is output at intervals of 8 cycles based on the clock signal.

Data output pattern bit F-1 in FIG.
Is "01", the output pattern determination circuit 59 in the common I / O 14a shown in FIG.
The "01" is detected and the output counter 62 is notified that the output is intermittent every 8 cycles.

Then, in the output system 60 of the common I / O 14a of the storage unit 14, after 19 cycles have elapsed after the reception of the first packet (for 1 bus) was completed, the first packet (for 2 buses) (storage) Output data from a common second bus 30
Up to the point where it is output, it is the same as in the case of continuous output, but since the intermittent output every 8 cycles is selected here, the next upstream second packet (from the storage unit is output after 8 cycles have elapsed). Output data: not shown) is output from the storage unit 14 to the common second bus 30. Then, after another eight cycles, the next upstream third packet (not shown) is output from the storage unit 14 to the common second bus 30, and the subsequent n-th (n is a positive integer of 2 or more) packet is also output. Similarly, data is output from the storage unit 14 to the common second bus 30 after 8 cycles.

Next, a case will be described in which the data to be output from the storage section 14 is output at intervals of 16 cycles based on the clock signal.

Data output pattern bit F-1 in FIG.
Is “10”, the output pattern determination circuit 59 in the common I / O 14a shown in FIG.
The "10" is detected and the output counter 62 is notified that the output is intermittent every 16 cycles.

Then, in the output system 60 of the common I / O 14a of the storage unit 14, after 19 cycles have elapsed after the reception of the first packet (for 1 bus) was completed, the first packet (for 2 buses) (storage) Output data from a common second bus 30
Up to the point where it is output, it is the same as in the case of continuous output, but since 16 cycles of intermittent output are selected, the next upstream second packet (from the storage unit is output after 16 cycles have elapsed). Output data: not shown) is storage unit 1
4 to the common second bus 30. Then again 1
After 6 cycles, the next upstream third packet (not shown) is output from the storage unit 14 to the common second bus 30, and the subsequent n-th (n is a positive integer of 2 or more) packet is similarly processed. After 16 cycles, the data is output from the storage unit 14 to the common second bus 30.

As described above, in the present embodiment, a bit designating the data output format is added to the empty bits of the downstream protocol (packet structure), and the storage unit 14 determines whether the output pattern is continuous output or not. Since it can be output by discriminating whether or not it is an intermittent output at every interval, even when reading and outputting a large amount of data, it is not necessary to wait for the output data of other processing units to finish reading, and the bus line Can be effectively used by improving the interoperability of.

In the fifth embodiment, the case where the data output pattern bit F-1 is 2 bits has been shown, but the present invention is not limited to this.
The value of data output pattern bit F-1 is 3 bits or 7
It may be applied to other arbitrary numbers such as the case of bits.

In each of the above embodiments, the number of common first buses and the number of common second buses is 17 respectively, but the present invention is not limited to this.
For example, it can be applied to the case where the number of bus lines is an arbitrary number such as 10 bus lines and 30 bus lines.

Further, in each of the above-mentioned embodiments, the case where the number of packet cycles is 9 cycles, or 7 cycles and 5 cycles is shown, but the present invention is not limited to this, and for example, 4 The present invention can also be applied to the case where the packet cycle number is any other number such as a cycle or 15 cycles.

In each of the above-mentioned embodiments, the number of bits of the primary destination ID is 6 bits, the number of bits of the secondary destination ID is 6 bits, and the number of command / data bits in one packet is 16 × 8 = The case of 128 bits or 64 bits, which is half thereof, or 96 bits has been shown, but the present invention is not limited to this. For example, the number of bits of the primary destination ID and the secondary destination ID is 8 bits. Or the command / data bit count is 48 bits or 256
It can also be applied to the case of any other number such as bits.

Further, in each of the above-mentioned embodiments, the description of the control circuit for each common I / O is omitted because it has little relation to the present invention, but an arbitrary control circuit is used for each part. Can be controlled.

[0151]

As described above, according to the present invention, a dedicated address (ID) is designated for the control unit and each processing unit, a protocol is set, and a primary destination ID is designated.
The control unit and a plurality of different processing units can be connected to a common bus.

Further, in the present invention, the secondary destination ID can be designated in addition to the primary destination ID, so that, for example, the data stored in the storage unit can be transferred to an external circuit without passing through the control unit, On the contrary, the signals or data generated by each processing unit are stored in the storage unit without going through the control unit, or the processing result of the processing unit designated by the primary destination ID is stored in the control unit. It is possible to directly transfer to the secondary destination ID without going through.

Further, according to the present invention, a common interface (I / O) for carrying out common protocol control is provided for the control unit, the storage unit, and the other processing units, and each unit is constituted by the common first bus and the common second bus. , The signal delay difference based on the wiring delay is eliminated, so that it is possible to eliminate the need to install a repeater for reducing the wiring delay. In particular, even when a wiring pattern is conventionally required for multiple layers, wiring can be performed only by the wiring pattern of the uppermost layer, and the design time can be shortened.

Further, according to the present invention, the entire integrated circuit can be simultaneously shifted to the power save state, and the power consumption can be reduced.

Further, in the present invention, since the circuit to be shifted to the power save state can be designated by the primary destination ID bit, only the arbitrary circuit can be brought into the power save state.

Further, in the present invention, since the power save command is used, it is possible to select and execute the power down state in which the power is saved to the entire integrated circuit and the standby state in which the power is saved except the interface section. it can.

Further, in the present invention, by inserting the command used in the secondary destination ID into the data / command bit in one packet, the amount of packets output from the control unit can be reduced. Moreover, the processing load of the control unit can be further reduced, and the total data transfer amount on the bus can be reduced.

Further, according to the present invention, the length of the packet used for transmitting signals and data can be set to the length optimized (optimized) for the storage unit and each processing unit. It is possible to improve the use efficiency of the bus such as the common second bus and the like, and also possible to improve the data transfer rate using the bus.

Further, in the present invention, a bit designating the output format of data is added to the empty bits of the downstream protocol (packet structure), and the storage unit outputs the output pattern continuously or intermittently at predetermined intervals. Therefore, even if a large amount of data is read and output, there is no need to wait for the output data of other processing units to be read, and interoperability of bus lines can be improved. It can be improved and effectively used.

[Brief description of drawings]

FIG. 1 is a first embodiment of a system LSI device according to the present invention.
It is a figure which shows the structure of.

FIG. 2 is a diagram showing a protocol (packet configuration) used in the common first bus shown in FIG.

3 is a diagram showing a protocol (packet configuration) used in the common second bus shown in FIG.

4 is a block diagram showing an internal configuration of a common I / O incorporated in a control unit or another functional unit of FIG.

5A to 5C are charts showing the timing of a packet signal composed of a 9-cycle pulse signal used in the first embodiment.

6A to 6C are charts showing the timing of a packet signal composed of a pulse signal of 9 cycles used in the first embodiment.

FIG. 7 is a diagram showing a protocol (packet configuration) used in a common first bus according to the second embodiment.

FIG. 8: Common I / O built in each part of the second embodiment
3 is a block diagram showing the internal configuration of FIG.

FIG. 9 is a diagram showing a protocol (packet configuration) used in the common first bus according to the third embodiment.

FIG. 10 is a diagram showing a protocol (packet configuration) used in a common second bus according to the third embodiment.

FIG. 11: Common I / O built in each part of the third embodiment
It is a block diagram which shows the internal structure of O.

FIG. 12 is a diagram showing a protocol (packet configuration) used in the common first bus according to the fourth embodiment.

FIG. 13 is a diagram showing a protocol (packet configuration) used in the common second bus of the fourth embodiment.

14A to 14C are timing charts of a packet signal composed of a 7-cycle pulse signal of FIG. 13 and a packet signal composed of a 5-cycle pulse signal of FIG. 12 used in the fourth embodiment. .

FIG. 15 is a diagram showing a protocol (packet configuration) used in the common first bus according to the fifth embodiment.

FIG. 16 is a diagram showing a common I / O incorporated in each part of the fifth embodiment.
It is a block diagram which shows the internal structure of O.

FIG. 17 is a block diagram showing a configuration of a main part of a conventional system LSI equipped with a protocol control type memory unit.

[Explanation of symbols]

8a 1st clock generation part, 8b 2nd clock generation part, 10 control part, 10a-14a common I / O,
11 first processing unit, 12 second processing unit, 13 n-th processing unit, 14 storage unit, 20 common first bus, 30
Common second bus 40a, 40b Clock signal line.

Claims (18)

[Claims] 1. A control unit is connected to a plurality of other functional units,
A common bus for transmitting signals of the respective parts; and a common interface part which is provided in each of the control part and the plurality of other functional parts and which transfers signals to and from the common bus by protocol control. The section is provided with a primary destination ID determination circuit for determining a primary destination ID inserted in a packet transmitted using protocol control via each of the common buses in the input system circuit. Semiconductor integrated circuit. 2. The common bus is a common first bus for transmitting a downward signal from the control unit to each functional unit, and a common second bus for transmitting an upward signal from each functional unit to the control unit. 2. The semiconductor integrated circuit according to claim 1, wherein the semiconductor integrated circuit has two systems. 3. The semiconductor integrated circuit according to claim 2, wherein the common first bus and the common second bus each have a dedicated clock generator. 4. Each packet transmitted via each common bus has a packet start control bit at the beginning of the packet to indicate that the first cycle of the packet begins. 3. The semiconductor integrated circuit according to item 3. 5. The common interface unit has an AND circuit for outputting the packet start control bit at an input timing of a clock signal from the clock generation unit, in an input system circuit. 4. The semiconductor integrated circuit according to 4. 6. Each packet transmitted via each common bus has a primary destination ID indicating a destination where the packet is processed after a packet start control bit of the packet.
6. The semiconductor integrated circuit according to claim 4, which has a bit. 7. The semiconductor integrated circuit according to claim 6, wherein the common interface section has a primary destination ID determination circuit for determining the primary destination ID bit in an input system circuit. 8. Each packet transmitted via each of the common buses has a primary destination ID bit of the packet followed by 1
8. The semiconductor integrated circuit according to claim 6, further comprising a secondary destination ID bit for transferring a processing result of the functional unit designated by the next destination ID bit. 9. The common interface unit includes a secondary destination ID register for storing the primary destination ID bit in an input system circuit, and an input system secondary destination ID register in the output system circuit. 9. The semiconductor integrated circuit according to claim 8, further comprising an output secondary destination ID register to which the secondary destination ID stored in is transferred. 10. The common interface unit selects a functional unit that first executes processing based on each packet by the primary destination ID, and is designated by the primary destination ID by the secondary destination ID. 10. The semiconductor integrated circuit according to claim 8, wherein the destination of the processing result in the functional unit is selected. 11. Each of the packets transmitted via the common bus has a power save bit for putting the semiconductor integrated circuit into a power save state in the packet. Alternatively, the semiconductor integrated circuit according to item 8. 12. The common interface section has a power save determination circuit for determining the power save bit in an input system circuit.
The semiconductor integrated circuit according to 1. 13. Each of the packets transmitted via each of the common buses has a command bit for storing a command for the functional unit designated by the secondary destination ID in the packet. Item 9. The semiconductor integrated circuit according to item 8. 14. The common interface unit has a first register for storing the command bit in an input system circuit, and a functional unit designated by the secondary destination ID in an output system circuit. 14. The semiconductor integrated circuit according to claim 13, further comprising: a second register for transferring the command bit, wherein the stored content of the first register is transferred to the second register. 15. Each of the packets transmitted via each of the common buses has a function unit which specifies the length of data / command bit for storing data or command in the packet by the primary destination ID. 9. The semiconductor integrated circuit according to claim 8, wherein the semiconductor integrated circuit has a variable length optimized for the processing content to be executed. 16. The common interface unit is an output system circuit, and a packet output to a functional unit designated by the primary destination ID is followed by a functional unit designated by the secondary destination ID. 16. The semiconductor integrated circuit according to claim 15, wherein the packets to be output are continuously output. 17. Each packet transmitted via each common bus either continuously outputs data from the functional unit designated by the primary destination ID in the packet, or 9. A data output pattern bit for intermittent execution is provided.
The semiconductor integrated circuit according to 1. 18. The semiconductor integrated circuit according to claim 17, wherein the common interface section includes an output pattern determination circuit that determines the data output pattern bit in an input system circuit.