JPH08202672A - Decentralized multiprocessing system - Google Patents

Abstract

PURPOSE: To decrease the frequency of copying of common data without increasing the load on the CPU of a master unit by writing data from the main bus side of the dual-port memory of a slave unit only by the master unit and reading out data only from the local bus side. CONSTITUTION: The master unit 2M and plural slave units 2S are connected thorugh a VME standard bus 1, and the 2-port memories 4 on the units 2M and 2S have common memory areas where the common data are stored. The addresses of the 2-port memory 4 on the slave units 2S on the side of the VME standard bus 1 are equally set among the slave units 2S. Data are written to the 2-port memories 4 from the side of the VME standard bus 1 only by the master unit 2M and read out only from the side of the local bus 3. Consequently, the traffic on the main bus is prevented from increasing and the throughput can be improved.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a distributed multi-processing system in which a plurality of processor units connected via a main bus carry out distributed processing.

[0002]

2. Description of the Related Art In recent years, in various plants such as buildings, factories, roads, electric power, and water treatment, in order to efficiently operate, maintain, and manage the plant, various equipment such as power receiving and distribution equipment, lighting, and disaster prevention equipment. Is centrally monitored and controlled by a remote monitoring and control system.

The remote monitoring control system is basically connected directly to the equipment to be monitored and controlled, and inputs monitoring information (display / measurement information) from the equipment to the control station (master station). Both a controlled station (slave station) that controls the equipment on the basis of various control information received from the control station and a control station that remotely controls and monitors the equipment via the controlled station. This is a configuration in which stations are connected by a communication line such as an optical cable. The central control station of this remote monitoring and control system is the transmission communication function, graphic panel and CR.
It has a wide variety of functions, including a function to combine with a T display. In today's world where the scale of target equipment and the sophistication of control functions are increasing, the data processing becomes more complicated with the single-processor method.Therefore, in the control station, distributed multi-processing that allows multiple processors to share the processing load. Systems are increasingly being adopted.

In addition to the remote monitoring control system described above, a distributed multi-processing system is now used in various other information processing fields.

FIG. 4 shows the basic configuration of the distributed multi-processing system. A VME standard bus 51 capable of constructing a multi-processing system is usually used as the main bus of this system. A plurality of processor units 52 ... Are interconnected via the VME standard bus 51. Each processor unit 5
2 is responsible for various processes such as monitoring process, communication process, and automatic control process. One of these processor units 52 ... Is a master unit (reference numeral 52M is added), and the other is a slave unit (reference numeral 52S is added).

Each of the processor units 52 has a dual port memory (hereinafter referred to as a 2-port memory) 54 which is accessible from both the VME standard bus 51 side and the local bus 53 side, and a CPU (Central Process).
sing unit) 55. The CPU 55 of each processor unit 52 uses the local bus 53 when accessing its own 2-port memory 54, and uses the VME standard bus 51 when accessing the 2-port memory 54 of another unit.

When the control station of the remote monitoring control system is configured as the above distributed multi-processing system, the CPU 55 of each processor unit 52 ... Real-time inputs / outputs information (hereinafter referred to as I / O information) in the system. Need to figure out. For example, when a certain processor unit 52 performs only a monitoring process and another certain processor unit 52 performs automatic control, each unit 52 performs its own process in real time based on the same I / O information. It is done. That is, the above-mentioned I / O information is shared data that is commonly used in each processor unit 52. Therefore, the same shared data must always be stored in the shared memory area of the 2-port memory 54 of each unit 52. I have to.

For example, the shared data input to the VME standard bus 51 of the system via an interface section (not shown) is taken into the master unit 52M, and the CPU 55 of the unit 52M stores the 2-port memory 54 via the local bus 53. The data is written in the shared memory area. When the shared data is updated in the master unit 52M in this way, the stored data in the shared memory area of the master unit 52M is immediately copied to the shared memory area of the 2-port memory 54 of the slave unit 52S. .

Conventionally, there are the following two methods for updating the shared data of the slave unit 52S after the shared data is updated by the master unit 52M.

As shown in FIG. 5, the master unit 5
The 2M CPU 55 accesses the 2-port memory 54 of each slave unit 52S via the VME standard bus 51 to update the data.

As shown in FIG. 6, the master unit 5
When the shared data is updated in 2M, the CPU 55 of the master unit 52M causes the slave units 52M to
An instruction to update the shared data is issued to the CPU 55 of S, and the CPU 55 of each slave unit 52S makes the VME
The 2-port memory 54 of the master unit 52M is accessed through the standard bus 51 to read the shared data, and the shared data in the 2-port memory 54 of each one is updated.

[0012]

However, in the above-mentioned conventional method, the CPU 5 of the master unit 52M is
5 has to update the stored data for each slave unit 52S, the load of the CPU 55 of the master unit 52M increases in proportion to the number of slave units 52S, and the copying of the shared data is performed by the slave unit 52S. Therefore, there is a problem in that the traffic of the VME standard bus 51 increases in proportion to the number of times.

Further, in the above-mentioned conventional method, although the load on the master unit 52M is reduced as compared with the above-mentioned method, copying of shared data is performed by the slave unit 5.
Since it is performed by the number of 2S, the problem that the traffic of the VME standard bus 51 increases in proportion to the number of the slave units 52S cannot be solved.

The present invention has been made in view of the above, and an object thereof is to reduce the number of times shared data is copied without increasing the load on the CPU of the master unit,
It is an object of the present invention to provide a distributed multi-processing system capable of preventing an increase in traffic on the main bus and improving the processing capacity.

[0015]

DISCLOSURE OF THE INVENTION A distributed multiprocessing system according to the present invention includes a central processing unit, and the central processing unit is connected by a local bus from both directions of a main bus side and a local bus side. Three or more processor units each having an accessible dual port memory are connected via a main bus, and the dual port memory of each processor unit stores shared data commonly used by each processor unit. A specific one of the three or more processor units having a shared memory area is a master unit that directly takes in the shared data input into the system and updates the shared data, and the other is the master unit. The shared data is updated so that it is the same as the data stored in the master unit. To solve the problems, it is characterized in that the following means are taken.

That is, the address of the shared memory area on the main bus side in the dual port memory of the slave unit is set to be the same for all slave units, and the data writing from the main bus side of the dual port memory of each slave unit is performed. Is performed only by the master unit, and data is read from the dual port memory of each slave unit only from the local bus side.

[0017]

According to the above construction, one master unit and two or more slave units are connected via the main bus, and the dual port memory on each unit is commonly used by each unit. A shared memory area for storing shared data is formed. The address of the shared memory area on the main bus side in the dual port memory on the slave unit is set to be the same for all slave units, and the writing and reading directions for the dual port memory are fixed. That is, data writing from the main bus side of the dual port memory of each slave unit is performed only by the master unit, and data reading from the dual port memory of each slave unit is performed only from the local bus side.

As a result, the shared data of the dual port memories on all the slave units can be updated by a single write operation from the master unit, and even if the number of slave units increases, the load on the master unit and There is no increase in main bus traffic.

[0019]

DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS The following will describe one embodiment of the present invention with reference to FIGS.

As shown in FIG. 2, the basic configuration of the distributed multiprocessing system according to this embodiment is such that a plurality of processor units 2 ... Are interconnected via a VME standard bus 1 as a main bus. is there.

Each of the above processor units 2 has the V
ME standard bus 1 side and local bus 3 such as VMX standard bus
2-port memory 4 accessible from both sides
The 2-port memory 4 is provided with a CPU (central processing unit) 5 connected via a local bus 3. The CPU 5 of each processor unit 2 uses the local bus 3 when accessing its own 2-port memory 4.
When accessing the 2-port memory 4 of another unit, the VME standard bus 1 is used.

In the 2-port memory 4 of each processor unit 2 described above, a shared memory area for storing shared data commonly used by each processor unit 2 is formed.

One of the processor units 2 ... Is a master unit (denoted by reference numeral 2M), and the other is a slave unit (denoted by reference numeral 2S). The shared data input to the VME standard bus 1 in this system via (hereinafter, referred to as I / F unit) 6 is first taken into the master unit 2M, and the CPU 5 of the master unit 2M uses its own two ports. The shared data in the memory 4 is updated, and the slave unit 2S
The shared data of the port memory 4 is updated in the same way as the self. Details of updating the shared data will be described later.

According to the standard of the VME standard bus 1, the addresses on the VME standard bus 1 side of the 2-port memory 4 of each processor unit 2 must be different from each other, but in this embodiment, all addresses are required. Slave unit 2
The addresses (addresses of the shared memory area) on the VME standard bus 1 side of the S 2-port memory 4 are set to be the same.

Then, as shown in FIG. 1, data writing from the VME standard bus 1 side of the 2-port memory 4 of each slave unit 2S is performed by the CPU of the master unit 2M.
5 only (VME from other units
(Data writing via the standard bus 1 is prohibited), and data is read from the 2-port memory 4 of each slave unit 2S only from the local bus 3 side.

The operation of updating shared data in the distributed multi-processing system having the above configuration will be described below.

When shared data is input to the VME standard bus 1 in this system from another device or unit through the I / F unit 6, the shared data is all master unit 2M.
Is taken into the CPU 5. Master unit 2M C
When the shared data is input via the VME standard bus 1, the PU 5 first writes the data to the required address in the shared memory area of its own 2-port memory 4 via the local bus 3 to write its own shared data. Update.

Next, the CPU of the master unit 2M
Numeral 5 simultaneously writes data to a predetermined address (address corresponding to the address updated above) of the shared memory area of the 2-port memory 4 of each slave unit 2S via the VME standard bus 1, and all data is written once. The shared data of the slave unit 2S is updated. This will be described in more detail below with reference to the timing chart of FIG. 3 showing each signal of the VME standard bus 1.

The CPU 5 of the master unit 2M is
First, after outputting a predetermined address that is set in common to the 2-port memories 4 of all slave units 2S to the address bus of the VME standard bus 1, the address
The strobe (AS *) is lowered (inverted from H level to L level) to enable the above address. next,
The CPU 5 of the master unit 2M is the VME standard bus 1
After the write data is output to the data bus of
The strobe (DS *) is lowered to make the above data valid. Furthermore, the CPU 5 of the master unit 2M
The write signal (WRITE *) on the control bus of the VME standard bus 1 falls. As a result, the data on the data bus is written to the designated address of the 2-port memory 4 of each slave unit 2S.

2-port memory 4 of slave unit 2S
When the writing is completed at, the DTACK signal (DTAC
K *) becomes L level, which allows the CPU 5 of the master unit 2M to recognize the completion of writing in the slave unit 2S. However, as in the present embodiment, writing is simultaneously performed in the 2-port memory 4 of a plurality of slave units 2S. If the slave unit 2S, which has the fastest response, falls, the DTACK signal falls,
The DTACK signal output of the other slave unit 2S is hidden (shown by the dotted line in FIG. 3). Even though the two-port memories 4 of the slave units 2S simultaneously write, depending on the state of the two-port memories 4 (for example, it may be used on the local bus 3 side, etc.), it may take some time to respond. It is unavoidable that there will be a gap. Therefore, each slave unit 2S does not output the DTACK signal immediately after the writing is completed, but delays the output timing of the DTACK signal slightly than usual in consideration of the delay of the response in the 2-port memory 4 of the other slave unit 2S. It is designed like this. By taking a margin in this way, the DTACK signal is output from the slave unit 2S, which has the fastest response, after the write operation of all the 2-port memories 4 is completed.

The CPU 5 of the master unit 2M is the DT
When the falling edge of the ACK signal is detected, the data strobe (DS *) is raised, the data output to the data bus is stopped, the address strobe (AS *) is raised, and the address output to the address bus is performed. Stop and start the write signal (WRITE *).

As described above, the CP of the master unit 2M
The shared data of all slave units 2S is updated by a single data write from U5.

The two-port memories 4 of the plurality of slave units 2S perform the write operation substantially at the same time,
Although a slight time shift occurs, since the DTACK signal is output from each slave unit 2S at approximately the same time, it is necessary to prevent a DTACK signal output short circuit between each slave unit 2S. Therefore, in this embodiment, DTAC
An output collector short circuit is avoided by using an open collector type buffer in the output section of the K signal.

As described above, the distributed multi-processing system according to this embodiment includes the CPU 5 and the CPU 5.
Is a VME standard bus 1 side and a two-port memory 4 accessible from both directions of the local bus 3 side, the processor unit 2 is
Three or more are connected via the ME standard bus 1, and the 2-port memory 4 of each processor unit 2 has a shared memory area for storing shared data commonly used by each processor unit 2, A specific one of the above processor units 2 is a master unit 2M that directly takes in the shared data input into the system and updates the shared data, and the other is the same as the stored data of the master unit 2M. In the system that is the slave unit 2S that updates the shared data so that the slave unit 2S has the same address in the shared memory area on the VME standard bus 1 side in the 2-port memory 4 of the slave unit 2S. VM of the 2-port memory 4 of each slave unit 2S
Data writing from the E standard bus 1 side is performed only by the master unit 2M, and data reading from the two-port memory 4 of each slave unit 2S is performed only by the local bus 3 side.

As a result, the data of the 2-port memories 4 on all the slave units 2S can be updated by a single write operation from the master unit 2M.
Therefore, unlike the conventional case, the load on the master unit 2M does not increase in proportion to the number of slave units 2S, and even if the number of slave units 2S increases, the load on the master unit 2M does not change at all. Also,
Unlike the conventional case, it is not necessary to copy (write operation) the shared data by the number of slave units 52S, and even if the number of slave units 2S increases, the copy is performed once for all slave units 2S at once. Since it suffices to do so, it is possible to prevent an increase in traffic on the VME standard bus 1.

Further, as described above, the slave unit 2S
By fixing the writing and reading directions of the 2-port memory 4 and efficiently using the VME standard bus 1 and the local bus 3 which are the main buses of the system, the processing capacity of the system can be improved.

The distributed multi-processing system of the present invention can be applied to a multi-processing system having a plurality of slave units 2S, that is, a multi-processing system having three or more processor units 2, and the number of units other than the above. There is no particular limitation.

Further, the distributed multi-processing system of the present invention can be applied in various information processing fields including, for example, a control station (master station) or a controlled station (slave station) of a distant monitoring control system.

The above-mentioned embodiments are intended to clarify the technical contents of the present invention, and should not be construed in a narrow sense by limiting to such specific examples. Various modifications can be made within the scope of the claims.

[0040]

As described above, in the distributed multi-processing system of the present invention, the addresses of the shared memory areas on the main bus side in the dual port memories of a plurality of slave units are set to be the same in all slave units. The data writing from the main bus side of the dual port memory of each slave unit is performed only by the master unit, and the data reading from the dual port memory of each slave unit is performed only from the local bus side.

Therefore, the shared data of the dual port memory on all slave units can be updated by one write operation from the master unit, and even if the number of slave units increases, the burden on the master unit and It is possible to improve the processing capability of the system without increasing the traffic of the main bus.

[Brief description of drawings]

FIG. 1 shows an embodiment of the present invention and is an explanatory diagram for explaining an operation of updating shared data in a distributed multi-processing system.

FIG. 2 is a block diagram showing a schematic configuration of the distributed multi-processing system.

[FIG. 3] V of the distributed multi-processing system
6 is a timing chart showing each signal of the ME standard bus.

FIG. 4 is a block diagram showing a schematic configuration of the conventional distributed multiprocessing system.

FIG. 5 is an explanatory diagram for explaining a shared data update operation in a conventional distributed multiprocessing system.

FIG. 6 is an explanatory diagram for explaining another shared data update operation in the conventional distributed multiprocessing system.

[Explanation of symbols]

 1 VME standard bus (main bus) 2 processor unit 2M master unit 2S slave unit 3 local bus 4 2 port memory (dual port memory) 5 CPU (central processing unit) 6 interface section

Claims (1)

[Claims] 1. A processor unit comprising a central processing unit and a dual port memory connected to the central processing unit by a local bus and accessible from both directions of a main bus side and a local bus side, Three or more are connected via a main bus, and the dual port memory of each processor unit described above has a shared memory area for storing shared data commonly used by each processor unit. One of them is a master unit that directly takes in the shared data input in the system and updates the shared data, and the other updates the shared data so that it becomes the same as the stored data of the master unit. In a distributed multi-processing system, which is a slave unit that The address of the shared memory area on the main bus side of the dual port memory of the same unit is set to the same for all slave units, and the data writing from the main bus side of the dual port memory of each slave unit is performed only by the master unit. The distributed multi-processing system is characterized in that data is read from the dual port memory of each slave unit only from the local bus side.