JPH05233437A - Memory sharing type multiprocessor system - Google Patents

Abstract

PURPOSE:To eliminate need for an arbitrating circuit which performs synthetic control over all processors and facilitated control, and to easily add a unit by laterally connecting a partial space memory to the unit of a processor through the arbitrating circuit. CONSTITUTION:This system consists of plural processor units each consisting of the partial space memory 1 formed by dividing a shared memory space and the processor 2. A gate 3 and the arbitrating circuit 4 which controls the gate 3 are provided between the processor units and other part spatial memory use request signals from all the processors 2 are inputted to each of the arbitrating circuits 4. When the use request signals are inputted repeatedly, the use requests are complied with according to previously set priority. Consequently, the arbitration is facilitated and the expansion of the system is made easy.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a tightly coupled multiprocessor system having a shared memory.

[0002]

2. Description of the Related Art In the multiprocessor system, it is necessary for the processors to mutually exchange information necessary for each processor to proceed with processing. From the viewpoint of a coupling method for realizing such inter-processor communication, it can be roughly classified into two types, a tightly coupled multiprocessor and a loosely coupled multiprocessor.

The tightly coupled multiprocessor can be realized by providing an interconnection network between a plurality of processors and a memory, as shown in FIG. 9 (a). As the number of processors increases, the contention for access to shared memory (conten
occurs and access becomes sequential, and the efficiency of parallel processing decreases.

In the loosely coupled multiprocessor, as shown in FIG. 9B, each of them has its own local memory (local memor).
y) and no global shared memory. Communication between processors is performed via a high-speed input / output port. Loosely-coupled multiprocessors do not cause memory competition, but if each processor relays communication, relay load becomes a problem.

In these shared multiprocessor systems, each processor operates by sharing a main memory, and the main memory can be directly accessed by each processor. But,
If the entire memory space is completely shared, the access traffic to the main memory becomes large, and a bottleneck occurs and the performance is degraded.

For this reason, the following measures are taken as shown in FIG. Each processor is provided with its own local memory that does not compete with other processors for access, and the shared area is limited to a part. The shared memory space is divided and each subspace is assigned to each processor.

[0007]

In such a system, when each processor accesses the shared space, an arbiter circuit that performs arbitration is required in order to avoid contention with other processors. If the number of processors (PE) is small, there will be no problem. However, if the number of processors (PE) is large, the scale of the arbiter circuit will be large and the control will be complicated.

The present invention has been made in view of the above problems, and an object of the present invention is to provide a memory sharing type multiprocessor system in which arbitration is easy and the system can be easily expanded.

[0009]

FIG. 1 is a block diagram showing the principle of the present invention. The present invention is a memory sharing type multiprocessor system including a plurality of processor units each of which is composed of a partial space memory 1 and a processor 2 in which a shared memory space is divided. An arbitration circuit 4 for controlling is provided, and each arbitration circuit 4 is configured to receive another partial space memory use request signal from all processors 2.

Further, when the use request signals are input redundantly, the use request is responded to by a preset priority order.

Further, the logical sum of the use request signals of all the processors 2 on the right side and the logical sum of the use request signals of all the processors 2 on the left side are input to each arbitration circuit 4. It was done.

Further, n processor units and n-1 arbitration circuits 4 provided therebetween are provided,
When referring to the partial memory 1 between the processor units of i and j (1 <i <j <n), only the gate 3 between i and j is opened.

[0013]

Although FIG. 1 shows the case of two processor units, a desired processor unit can be connected by adding these to the left and right. In the case of FIG. 1, when each processor refers to its own memory 2, the arbitration circuit 4 closes the gate 3 and the other memory 2
When referring to, the gate 3 is opened.

FIG. 2 shows the logic for opening and closing the gate shown in FIG. lock-A and lock-B are access requests to the other memory, and 1 is requested and 0 is not requested. In the case of (1, 1), the priority right is granted to the processor 2 on the left side, which is the same as (1, 0) in this case.

Further, when both the left and right processors 2 issue a reference request for the memory 1 of the other party, the arbitration circuit preliminarily determines the priority order to be used in case of conflict. In the case of FIG. 1, for example, priority is given to the processor 2 on the left side,
First, the left processor 2 refers to the right memory 1, and then the right processor 2 refers to the left memory 1.
This also applies when there are three or more processor units,
For example, the highest priority is given to the processor 2 at the left end, and the priority is lowered in order toward the right.

Further, to each arbitration circuit 4, the logical sum of the use request signals of all the processors 2 on the right side and the logical sum of the use request signals of all the processors 2 on the left side are inputted. In this way, the number of processor units can be easily increased.

Further, when the memory 1 is referred to by the processor 2 of i, j, only the gate 3 between the processors 2 of i and j is opened, and the gate 3 between 1 and i and the gate between i and n. By making 3 closed, the processor 2 in the closed section can access its own memory 1.
As a result, it is possible to minimize the influence of one processor 2 referring to another memory 1 on another processor 2.

[0018]

Embodiments of the present invention will be described below with reference to the drawings. FIG. 3 shows a block diagram of the first embodiment of the present invention. Reference numeral 1 is a partial space memory obtained by dividing a shared memory space, 2 is a processor, 3 is a gate that enables input / output between the partial space memories 1, and 4 is an arbitration circuit that controls opening / closing of the gate 3. Input the use request signal of. Reference numeral 5 is a gate provided for each processor 2.

Next, the operation will be described. FIG. 4 shows the logic of gate opening / closing. In FIG. 4, lock-A, lock-B
Is a use request signal to the other partial space memories 2 output from PE-A and PE-B, respectively. 0 indicates that there is no lock signal, and 1 indicates that there is a lock signal. When the lock signal is output from both PE-A and PE-B, in the case of (1, 1), P
EA has priority, and therefore the gate opening and closing is the same as in (1,0). In the case of (1,1), MEM of PE-A
PE-B is the ME only after the access to -B is completed.
I cannot access M-A.

Next, a second embodiment will be described. FIG. 5 is a diagram showing the configuration of this embodiment. This embodiment is the first shown in FIG.
Examples include memory MEM-C, gate GATE-F, processor
PE-C is added, and therefore GATE-B and arbitration circuit AB-B are added. AB-A has a lock signal from PE-A on the left side and PE-B, PE on the right side.
The logical sum of the -C lock signal is input. AB-B receives the logical sum of the lock signals of PE-A and PE-B on the left side and the lock signal from PE-C on the right side.

Next, the operation will be described. FIG. 6 shows the gate opening / closing logic of this embodiment. Priority is PE-A, PE-
B and PE-C are given in this order. Therefore (0,1,0)
And (0,1,1) are in the same gate open / close state. Also, (1,0,0), (1,0,1), (1,1,0),
(1,1,1) is in the same gate open / close state. GA
TE-E is determined by the logical product of lock signals of both GATE-Ea and GATE-Eb. For example, when (1,0,0), GATE-E
Since a is closed and GATE-Eb is open, GATE-E is closed ×
Open = closed.

The opening and closing of the gate is performed with a signal of 1 bit. If this is made up of a plurality of bits, more complicated opening / closing processing becomes possible. For example, in the example shown in FIG.
-A is unrelated when accessing MEM-B GATE-B
Is open and GATE-F is closed. For this reason, the PE-C cannot access its own memory MEM-C, but it can be controlled so as to prevent such a situation and open or close the gate only in the use range.

Next, the third embodiment will be described. FIG. 7 shows the configuration of this embodiment. This embodiment is different from the second embodiment shown in FIG. 5 in that it has a memory MEM-D, a gate GATE-G, and a processor PE-.
D and gate GATE-C, arbitration circuit AB-C
Is added. Along with this, PE-C and PE-D lo
OR gate for transmitting ck signal to the left side, PE-A, PE-B,
An OR gate for transmitting the PE-C lock signal to the right side will also be added.

Next, the operation will be described. The arbitration circuits AB-A, AB-B and AB-C have gates GATE-A and GA according to the logic similar to that shown in FIG.
Controls TE-B and GATE-C. Also gate GATE-D, GA
TE-G opens and closes according to inputs a and b, and gate GATE-E,
GATE-F opens and closes according to the logical product of inputs a and b.

For example, consider a case where PE-B wants to access a memory (for example, MEM-D) belonging to another PE. PE-B
Outputs the lock signal to the OR gate. Although the lock signals from PE-C and PE-D are not active in the OR gate, the lock signal from PE-B has changed to active, so the lock signal is changed to arbitration circuit AB.
-A, output to gate GATE-D. In GATE-D, the gate is closed by the input of the lock signal and the bus of the memory MEM-A is opened. Arbitration circuit AB-A, PE-A
Although the lock signal is not output, PE-B outputs the lock signal, so open GATE-A.

Similarly, GATE-E operates by PE-A and the output of the OR gate, but PE-A, PE-C, PE-
Since D does not output the lock signal, the gate is opened and PE-
The address of B is output to the memory bus. Similarly, GATE-B and GATE-C open the gate, and GATE-F and GA
The TE-G closes the gate and the shared memory bus passes only the signal of PE-B, so that PE-B can access the memory MEM-D.

In this example, the case where the lock signal is 1 bit has been described. For this reason, PE-B is opening GATE-A and closing GATE-D, which are unnecessary for accessing MEM-D. This can be prevented by performing the lock signal with a plurality of bits as described above.

Next, a fourth embodiment will be described with reference to FIG. This embodiment is different from the third embodiment shown in FIG. 7 in that the memory MEM-
E, Gate GATE-I, Processor PE-E and Gate GATE-
H, arbitration circuit AB-D is added. Along with this, the OR gate which transmits the lock signal of PE-D and PE-E to the left side, and PE-A, PE-B, PE-C, PE-D
Increase the OR gate that transmits the lock signal to the right.

Regarding the operation, an arbitration circuit AB-C, AB-D and a gate are provided by an OR gate.
Signals for controlling GATE-H and GATE-I need only be generated from the PE-E lock signal and the signals from PE-A to PE-D. As described above, the present invention can configure a shared memory type multiprocessor system without providing an arbitration circuit for uniformly controlling all PEs.

[0030]

As is apparent from the above description, the present invention has a configuration in which the subspace memory and the unit of the processor are horizontally connected via the arbitration circuit, and requires an arbitration circuit for uniformly controlling all the processors. Since it does not, the control is simple and the addition of units can be easily done.

[Brief description of drawings]

FIG. 1 is a principle block diagram of the present invention.

FIG. 2 is a diagram showing the gate opening / closing logic of FIG. 1;

FIG. 3 is a circuit diagram of a first embodiment of the present invention.

FIG. 4 is a diagram showing a gate opening / closing logic of the first embodiment.

FIG. 5 is a circuit diagram of a second embodiment.

FIG. 6 is a diagram showing a gate opening / closing logic of a second embodiment.

FIG. 7 is a circuit diagram of a third embodiment.

FIG. 8 is a circuit diagram of a fourth embodiment.

FIG. 9 is a diagram illustrating a tightly coupled and loosely coupled multiprocessor.

FIG. 10 is a diagram illustrating an example of a conventional tightly coupled multiprocessor.

Claims (4)

[Claims] 1. A memory shared multiprocessor system comprising a plurality of processor units each comprising a partial space memory (1) obtained by dividing a shared memory space and a processor (2), and a gate (3) between each processor unit. An arbitration circuit (4) for controlling the gate (3) is provided, and each arbitration circuit (4) is configured to receive another partial space memory use request signal from all the processors (2). A shared memory multiprocessor system. 2. The memory sharing type multiprocessor system according to claim 1, wherein when the use request signals are input in duplicate, the use request is responded to in a preset priority order. 3. Each of the arbitration circuits (4) has a logical sum of the use request signals of all the processors (2) on the right side and the logic of the use request signals of all the processors (2) on the left side. The memory sharing type multiprocessor system according to claim 1, wherein a sum is input. 4. The processor comprises n processor units and n-1 arbitration circuits (4) provided therebetween,
When the partial memory (1) is referred to between the processor units of i and j (1 <i <j <n), only the gate (3) between i and j is opened. The memory sharing type multiprocessor system according to claim 1.