JPH021037A - Control of response by user of mutual communication bus - Google Patents

Abstract

PURPOSE: To regulate a line scramble interval and a use signal interval with state machines connected to respective users by giving a multiplex channel execution order designation bus where the respective users are connected to respective channels and the priority record of the users, which shows the present priority state of the connected user as against the other users. CONSTITUTION: An access control system 10 contains the execution order designation bus 21 having the channels, a control bus 22 and a bus system clock 23. The clock 23 generates and transmits timing signals synchronizing the whole bus system and regulating final time increase to all the bus users. A representative user 12 is connected to an access control circuit 17 connected by a bus request line 19 and a permission line 20, to a mutual communication bus 14, the control bus 22 and the clock 34. The bus 21 is connected through a mutual connection key 24, and the other users 13 are similarly connected to the respective lines. Then, the priority record of the users 12 and 13 is give.

Description

DETAILED DESCRIPTION OF THE INVENTION A computer system can be organized with multiple processors operating simultaneously in parallel.

In such systems, the multiple processors operate in a largely independent manner, although it is sometimes necessary to transfer information between the processors or between the processors and other system components, such as input/output devices.

To perform these information transfers, intercommunication buses are provided that connect to the processor and other system components. This bus can transfer information from any user to any other user. Although such a bus is very flexible in its operation, there must be some procedures to ensure orderly use of the intercommunication bus. The present invention relates to controlling access to an intercommunication busbar shared by several users to provide orderly use of the busbar by multiple users.

The present invention provides a multi-channel performance ordering (arbitration) bus in which each user is bound to one of its separate channels, and for each user indicating the current priority status relative to each other of the bound users. It is characterized by priority records. The contention interval and signal usage interval are defined by a state machine associated with each user. During the line contention interval,
Each user wishing to use the intercommunication bus then bids for its use by transmitting a bus request signal.

Each user performs an analysis of the bus request signal to see if it has a dominant priority to use that intercommunication bus for a transaction, and access is granted accordingly. During the busy signal interval, the user currently using the intercommunication bus transmits a busy signal.

The busy signal is used by each user to update its priority record, so that the last user is subordinated to all others for the next send request to initiate a transaction. It will give priority.

For transactions that require a response from some system user other than the user initiating the transaction, a second round of bids is made to determine whether any user is eligible to respond. It also determines which, if any, are enabled to do so. If the response send request does not indicate any requestor, the system immediately initiates a send request for a new transaction; if there is one or more eligible responders, one is selected and made available for reply. be done.

DESCRIPTION OF THE PREFERRED EMBODIMENTS Referring to the drawings, an access control system 10 according to the present invention controls the use of an intercommunication bus 14 by processor users 12.13 and input/output devices 16. Information is transferred on the intercommunication bus in predetermined related sequential or parallel operations called transactions.

There may be multiple types of transactions with separate operations such as reading or writing to the cache memory of other processors, acknowledging interrupts, and reading or writing to input/output devices. In particular, the access control system shown in FIG. An execution priority bus 21 having a bus system clock 22 and a bus system clock 23 is included.

The bus system clock generates and propagates timing signals to all bus users that define the final time increment that synchronizes the entire bus system. The clock is a primary periodic signal (A clock) whose rising edge defines the start of a new time increment for all bus terminals.
to spread the word. The clock also propagates a secondary signal (B clock) phase-shifted from the A clock, with a rising edge defining one time toward the end of each time increment.

The B clock is generally used to allow signals into the latch after the ledger transient has subsided. The clock signal is shown in FIG.

A representative user 12 is connected to an access control device 17 by a bus request line 19, a response ready line 50, a grant line 20, and a response enable line 51.
and to the intercommunication bus vA 14, the control bus 22 and the bus system clock 23. Access control device 1
7 is directly connected to control bus 22 and bus system clock 23, and is also connected to execution order designation bus 21 through interconnection key 24. The user 12 along with the access control device 17 includes an interconnection key 24 and an initialization key 3.
8 and the intercommunication bus 14 through a standard boat 47 . Other users, including user 13 and input/output device 16, are connected similarly to user 12.

The access control device 17 includes a transmission line 25, (n-1
) monitor lines 26, control circuit 27, drive circuit 2
8. Priority state storage device 29, execution order designation logic 30
, an access grant circuit 31 with grant latch 37, an update circuit 32, a no-send request circuit 33, an initialization gate 39, and an update gate 34 are included interconnected as shown in FIG.

Details of priority state storage 29 and execution order designation logic 30 are shown in FIG. Priority state storage device 2
9 includes (n-1) two-state storage elements 35, preferably flip-flops. The output from the memory element 35 passes in parallel to (n-1) AND gates.

A monitor line 26 also runs in parallel to the AND gate. The output of AND gate 36 is combined with signal T on transmission line 35 to produce signal P, as shown.

In particular, the update circuit 32 shown in FIG. 7 connects the transmission line 25 to the set input of each of the two-state storage elements 35 and connects the monitor line 26 to the reset input of each of the storage elements 35, respectively.

These connections are made through update gate 34. An output line 40 from the initialization key 38 is connected through an initialization gate 39 to the SEFF and reset input terminals of the storage element 35 .

Control circuit 27 includes a circular state machine that controls the operation of access control device 17 and tracks what is happening on the intercommunication bus. The operation of this state machine is illustrated in FIG. 6 and is further detailed in connection with system operation.

The access control device 18 and the additional access control device are the same as the access control device 17.

Turning to the operation of the system, users typically use their own local cache memory and their own synchronized clocks that do not belong to the bus or other users. Manipulate processing instructions independently. At times, performed computations may generate requests to exchange information with other system components. Typical events that require information exchange are:
The need for data stored in a user's cache memory, the need to update data stored in other users' memories, and the need to obtain information from input/output devices to handle interrupts. Information is exchanged on the intercommunication bus within one transaction. There may be several types of transactions, but each will have a fixed format that defines what is transmitted on which bus components and in what order. In the system described herein, the format requires that signals identifying the transaction type be passed on the control bus and detailed information such as addresses and data be passed on the intercommunication bus. When a user needs to communicate on the bus system, he loads information into the busbar to maintain transactions and then tells his access control device 17 that whenever it requests the use of the intercommunication bus, he A bus request signal R is transmitted on the bus request line 19 indicating that it is ready to start. When a grant signal G is received from the access controller 17 on the grant line 20, the user initiates a bus transaction.

Users also constantly monitor the busbars to detect signals indicating that transactions initiated by other users require the monitoring user to specify a response. When the user detects such a signal, it loads the response into the buffer buffers and issues a response ready signal R' on line 50 to its controller 17 if these buffers are ready. Then, when a response enable signal E on line 51 is received on line 15, the user begins transmitting the response.

The operation of the access control device 17 is organized by a control circuit 27, which can be understood with reference to its state machine shown in FIG. This state machine transitions from state to state through a loop that transfers from one state to the next at the beginning of each time increment marked by the A clock. .

It is convenient to follow the operation of the state machine from the point at the top of the diagram, just entering shape Bc.

The presence of a state machine in state Bc defines a contention interval during which control circuit 27 issues an active C signal. This signal is applied to the drive circuit 28, access permission circuit 31, and non-transmission right request circuit 33 as shown in FIG. At the end of the time increment marked by the A clock, if the control circuit 27 receives the no-transmit request signal X from the no-transmit request circuit 33, it re-enters the state pc; in the absence of the no-transmit request signal. If so, it moves to state U. C and clock signals are shown in FIG.

The presence of a state machine in the state QU defines a usage signal interval during which the control circuit 27 issues an active C signal as shown in FIG. As shown in FIG. 2, the C signal is applied to access grant circuit 31 to update gate 34. During the time increment that the state machine resides in the U state, the control circuit receives a signal from the control bus 22 indicating what type of transaction is being initiated by one of the users 12. According to these received signals, at the end of the period, the state machine branches into one of a plurality of transaction completion states, called Z, each corresponding to one of the predefined transaction types.

Transaction types A and B are representative of fairly simple transactions, such as performing a transfer of data from an initiating user to an input/output device. Longer and more complex transactions can also be defined and used as exemplified by transaction type C. For every transaction, the state machine continues through one successive transaction completion state chain as needed to complete the particular transaction in progress. When a state machine reaches the end of any chain it is following,
It returns to state C and begins another contention interval.

Type D branch chains are of particular relevance to the present invention. An example of such a transaction is
There are interrupt acknowledge transactions that can occur when a processor user initiates a type D transaction to maintain interrupts and obtain needed information. At the time of branching according to type D transaction,
The state machine inputs state C'. The presence of the state machine in state C' defines the response right request interval, the amount of which control circuit 27 issues an active C' signal. This signal is transmitted to the drive circuit 2 as shown in FIG.
8, applied to the access permission circuit 31 and the non-transmission right request circuit 33.

At the end of the time increment for existence in state C' (
If the control circuit 27 (marked by A clock) receives the no-transmission right request signal X from the no-transmission right request circuit 33, it re-enters state C; if there is no no-transmission right request signal, this The state moves to state Bv.

The presence of the state machine in state 1 defines a response enable interval during which the control circuit 27 issues a V signal. This signal is applied to the access grant circuit 31 as shown in FIG.

■ At the end of its cycle in the state, the state machine
Return to state Bc shown at the top of the figure.

The control circuit 27 is also responsive to a "wait" signal received from the control bus during any state, re-entering one state machine rather than proceeding to the next state. let This feature allows users who are not ready to keep up with standard transactional bases to slow down the advancement of the state machines in all controllers by transmitting a wait signal on the control bus.

The state machine's operation depends on the signals received from the control bus, but it does not care where the user sends these signals. As a result,
The multiple access control device state machines are in separate but identical harmonized records of the state of the intercommunication bus.

Consider now the interaction of the signals issued by the control circuit with the other elements of the access control device. To simplify this discussion, it is assumed that the signals on the (n-1) monitor lines are called Mi and that i varies from 1 to (n-1).

The signal of the storage element 35 is called Si with the storage element index matching that of the monitor line connected to the same one of the AND gates 36.

When the C signal issued by the control circuit during the line contention interval is applied to the control circuit 28, it indicates on line 19 that the user 12 is requesting use of the intercommunication bus.
This would cause the bus contention signal to be transmitted through the interconnect key 24 to the ranking bus channel associated with this user.

Similarly, during the contention interval, the contention signals transmitted on the priority bus are applied to the priority designation logic 30 where they are logically parsed with the signals from the priority status store 29. , generates a signal P indicating whether the router 12 has the dominant priority or not. The active state condition on the execution priority specified bus channel is 1, the inactive state condition is 0, and the storage element S of the priority state storage device is
Assuming that the two states of i are named similarly, the logical operation of the execution ordering logic can be written in the form of a modulo 2 operation as follows: P=T(M+S+”l
)(MzSz +1)...(L-1sfi
-+ ”1).

The C signal, along with the B clock applied to the access grant circuit 31, is connected to the P to grant latch 37 during the second half of the contention interval.
Perform signal acquisition. The line contention signal from the execution order designation bus is also applied to the no-transmission right request circuit 33 where it is analyzed, and the result is
issued as a signal. The X signal provides control circuit 27 with a reference for immediately resuming the contention interval.

The U signal issued by the control circuit during the use signal interval is applied to the access grant circuit 31 and when the W signal from the grant latch 37 is asserted, this causes the C signal to be applied to line 20.
It will be sent to user 12 above. On the other hand, the G signal causes the drive circuit 28 to issue a T signal. The U signal, along with the B clock, is applied to the update gate 34 to cause the update of the borrow rank storage element to take place during the second half of the usage signal interval.

The control circuit 27 is also responsive to initialization signals received on the control bus and enables the transfer of signals through the initialization gate 39 from the initialization key 38 to the priority state storage 29. do.

C' issued by the response transmission right request interval amount control circuit.
Applied to the double signal drive circuit 28, this means that if the user sends a response ready signal R' on line 50 indicating that he or she is ready to respond on the interconnect bus, the interconnect key 24 The response transmission right request signal is transmitted to the execution order designation bus channel associated with the user through the execution order specification bus channel.

Similarly, during the response transmission right request interval, the response transmission right request signal transmitted on the execution priority designation bus is transmitted to the execution priority designation logic 3.
0, where these are priority state stores 2
9 is logically analyzed to produce a signal P indicating whether the user 12 has the dominant priority or not.

This analysis is as described in connection with contention interval.

The signal issued by the control circuit during the response enable interval is applied to the access grant circuit 31 and the grant latch 37
If the W signal from
A signal will be sent on line 51 to user 12.

Consider now a global organization in which multiple access control devices interact with each other. Multiple control devices all have a structure,
Note that they are operationally the same. The only difference between the controllers is the interconnection key through which the controller is connected to the execution priority bus, the information content of the priority state store, and the initial value of the priority state store. It's in the initial settings key.

Interconnection key 24 interconnects execution priority bus 21 with access control device 17, particularly as shown in FIG. In contrast to the control devices 17, which are all similar, the interconnection keys and initialization keys are different and organized into a pattern on a global basis. Each key has n connections on its bus side that are connected to n execution order designation bus channels (referred to as AI, At, . . . A7). Each interconnection key connects transmission line 25 on its controller side.
(signal T) and (n-1) monitor lines 26 (signal Mi) of its associated control device.

A first interconnection key (referred to as K) connects A to its transmission line and connects (n-1) bus channels other than A1 to the (n-1) monitor lines of its controller. a second interconnection key (K2) connects A2 to the transmission line and connects (n-1) busbar channels other than A2 to (n
-1) It has an internal connection part that connects to the monitor line of the book. And so on throughout the interconnect key. In particular, each control device's transmission line is keyed (Ki).
) to the individual bus channel Ai. A connection diagram is shown in FIG.

In particular, the initial setting key 38 as shown in FIG.
Priority state storage 29 through initialization gate 39
generates signals from the power supplies (0 and +) that are applied directly or in reverse order to the set and reset inputs of the storage elements 35 of.

In the first initialization key (Ii) (associated with the access control device I and the interconnection key (K, )), the connecting part applies ten voltages to all reset inputs of the storage elements and to any one of them. This is not applied to the set input terminal of the access control device 1, and thus the initial setting gate 39 of the access control device
is such that when it allows these signals, all of its storage elements will be reset to zero.

In the second initial setting key I2, the connection part is the first
A positive voltage is applied to the set input terminal of the memory element of , and the reset input terminal of all the memory elements with a higher index, so that when the initialization gate 39 of the access control device 2 accepts these signals, one of the memory elements of that memory element The first one is set to 1, such that storage elements with higher indexes are to be reset to 0. (The indexing of the storage elements is the same as that of the associated monitor lines and signals as assigned during the discussion of the interconnect key).

In the third initialization key, the connection part applies a voltage of 10 to the set input terminals of the first and second storage elements and to all reset input terminals of the higher indexed storage elements, thus controlling the access. When the initialization gate 39 of the device 3 accepts these signals, the first and second of its storage elements will be set to 1 and the further indexed storage elements will be reset to 0. It's something like this.

The connection pattern continues to the higher indexing default key with the switching position increasing gradually for the higher indexing default key below which a voltage of ten is applied to the set input. . If the nth initialization key has a switching position above the highest indexed storage element, then all of that storage element will be set. - Boat fishing patterns are shown in the table below.

Where key is n n -
For purposes of discussing global aspects of the operation of the present invention, priority state storage 2 is not used in discussing the internal operation of a single controller.
It seems appropriate to use different rules for identifying the signals of the 9 storage elements. Storage element signals are named based on their connection to the execution priority bus. Each storage element is connected to two different channels (differently). The storage element signal is designated Sij, which means that it is in the access control device with the T line connected to the bus channel Ai through its interconnection key and connected to the same AND gate 36 as the channel Aj.
This means that it is connected to channel Aj. AND gate 36
Since Sij is never connected to the same bus channel as T, Sij is constrained by the condition i not equal to j.

The signals stored in the priority state memory of each controller primarily indicate the current priority of that controller relative to each other controller.

That is, if Sij is 1, this indicates that control device 3 has dominant priority over control device 1. Although any combination of values can occur within the (n-1) storage elements of a single controller, all global combinations of values of n(n-1) system elements It may not necessarily be consistent with the prioritization. The global conditions that storage devices must satisfy to reflect orderly prioritization of controllers are Sij
is not equal to Sji, and the number of things in the memory of either controller is different from those in any other device. The organization of initialization keys ensures that these conditions are met at the beginning of operation, and the organization of interconnection keys ensures that all update changes maintain the required conditions.

From a system perspective, each controller tracks its priority status relative to each other controller in its priority store.

Then, at the beginning of the contention interval, each controller:
When seeking to initiate a transaction on an interconnect bus, transmission on its own priority channel (i.e., the channel to which it is only bound by a connection through its interconnect key) will cause all other Announces a transmit right request to the device. Towards the end of the contention interval, each controller, through its priority logic, analyzes the transmission request signal and determines which controller should be granted access to the intercommunication bus.

In successive signal intervals of use, the control device requesting the granted transmit right of access allows its user to initiate transactions on the intercommunication bus and also transmits T signals on its own channel. This signal tells all other control devices about this use. Towards the end of the usage signal interval (at time B clock), a signal indicating which controller has used the intercommunication bus is sent through the update gate on the priority bus to update the priority record. used for. The controller in use modifies its record to indicate that the controller in use now controls it; each controller that is not in use modifies its record to indicate that the controller in use now controls it. record that it is subordinate to These modifications result in the last used control being moved from its previous position to the bottom of the priority order, otherwise the priority is left unchanged.

System operations thus enforce a policy of having the last initiator of a transaction go to the end of the priority line.

When dealing with different kinds of transactions that require responses and can have one, multiple, or n qualified responders, each qualified responder has the right to send responses on its own priority channel. Transmission of a request signal results in one response right request interval indicating readiness to respond. All of these signals placed on the priority bus during this response request interval are analyzed to determine whether any responders are making send requests and, if so, which ones have priority. decide. If there are no qualified responders, the system resumes contention for new transactions without delay; if there are one or more qualified responders, one of them is enabled to respond. Operations during the response request interval follow the pattern of those during the contention interval and obtain economic benefits using the same access controller circuitry. By immediately resuming primary line contention for new transactions when there are no bids for a response, the system avoids hogging the bus with an answer that never comes.

The reply send right request operation does not modify the priority storage information and therefore does not interfere with the priority policy, which gives priority to the oldest users in initiating a transaction.

In most of the foregoing descriptions, it is assumed that a constant number of users all have requests to use the intercommunication bus, i.e., for a system with n priority channels, there are n actively requesting the right to send. It was assumed that there was a user making the request. The system works equally well if there are fewer than n users, or if there are some passive users who participate in transactions but do not initiate any transactions. In such cases, the nominal priority of passive or non-existent users is elevated to the highest priority, but since these users never request transmit rights to the intercommunication bus, the bus grant is always the highest transmit request priority. This is done for users.

The above-described system facilitates compatibility of users operating on intercommunication buses because the control equipment is identical. Thus one intercommunication bus may be designed with only one connection and initialization key terminating in one control device and a standard port to which users with different functions can then be connected. It can be connected to any boat without discrimination.

[Brief explanation of the drawing]

FIG. 1 schematically depicts an access control system for controlling responses by multiple bus users of an intercommunication bus according to the invention. FIG. 2 shows, in block diagram form, an access control device used in the response control system of FIG. FIG. 3 shows details of the priority status storage and execution order designation logic used within the access control system of FIG. FIG. 4 details the structure of the interconnect key used within the access control device of FIG. FIG. 5 shows timing signals used within the access control device of FIG. FIG. 6 illustrates the operation of the state machine used in the present invention. FIG. 7 shows the connection of the update circuit of the access control device of FIG. 2. FIG. 8 shows a connection diagram of the interconnection keys of the access control system of FIG. Number of main components 10 - Access control system, 12.13 - Processor user 14 - Busbar, 16 - Input/output device, 1.2.
3.17.18 - access control device, 19 - bus request line, 20 - grant line, 21 - execution order designation line, 22 - direct control bus, one bus system clock, one interconnection key 25 - transmission line, - monitor line, 27-control circuit, -drive circuit, 1-priority state storage device, 1-execution order specification logic, 1-access permission circuit, 32-update circuit, -non-transmission right request circuit, 34-update gate, -2 state storage Element, 36-
AND Gate, - Grant Lunch, 38 - Initialization Key - Initialization Gate, 40 - Output Line, - State Machine, 50.51 - Line. Procedural amendment (method) % formula % 1. Indication of the case Patent Application No. 294451 of 1988 3. Person who makes Mf correction Related to the case Applicant 4, Agent 5, Date of amendment order - F1 year 3Rqrs ( 1 haiku meeting!-kito 3t! 1 yoshi)

Claims (10)

[Claims] (1) A method for controlling responses by a plurality (P) of bus responders to an intercommunication bus that provides for the transfer of information in prescribed transactions between bus users, comprising the steps of: with each of said responders; n channels to communicate (n is P
and above); associating each responder with a separate one of said channels; and for each responder, an associated response to each other responder. maintaining a priority state record indicating the current priority state of the user; initiating a transaction on said intercommunication bus specifying a requested response; defining a response right request interval, in which: transmitting one response right request signal from each of said responders then eligible to respond on its associated channel; performing an analysis of the response right request signal for each responder so that the responder can determining whether it has dominant priority; enabling the responder whose analysis indicates that it has dominant priority to respond on the intercommunication bus; (2) said priority state record for each particular responder is maintained in its own set of (n-1) two-state storage elements, the storage element states being designated as 0 or 1; , each storage element is associated with a respective channel that is not associated with a particular responder;
and the analysis ascertains whether a particular responder has a dominant priority for responding using the following logical function: P=T (M_1S_1+1) (M_2S_2+1)...
(M_n_-_1, S_n_-_1+1) In the formula, T
represents a 0 or 1 signal from the execution priority bus channel associated with a particular responder, M_i represents a 0 or 1 signal from the i-th channel not associated with a particular responder, and S_i represents a 0 or 1 signal from a particular responder's storage element, and the operation shown is a modulo 2 operation. (3) The value of the state of the two-state memory element is related to the j-th responder, and the value of the two-state memory element in the set associated with the i-th responder is related to the i-th responder. the value of the two-state storage element in the set associated with the jth responder is not equal to the value of the two-state storage element, characterized in that the number of 1's in each responder's priority state record is different. , the method according to claim 2. 4. The method of claim 3, further comprising the step of: (4) restarting another transaction immediately if no response right request signal is issued during the response right request interval. (5) control access by multiple (P) bus users to an intercommunication bus that provides for the transfer of information between users in defined transactions to provide for orderly use of the intercommunication bus, including the steps of: A method of: providing an execution ordering bus having n channels (where n is greater than or equal to P) communicating with each of said users; associating each user with a different one of said channels; each user maintaining a priority state record indicating the current priority state of the associated responder with respect to each other responder; initiating a transaction on the intercommunication bus specifying the requested response; defining a line contention interval in which a bus contention signal is transmitted on its associated channel from each of said users then seeking use of said intercommunication bus; for each user, said bus performing a contention analysis of the contention signal to determine whether the user has a dominant priority; intercommunicating the user for which the contention analysis indicates that the user has a dominant priority; granting access to the bus; defining a busy signal interval in which a busy signal is transmitted on the associated channel from any of the users then using the intercommunication bus; performing an in-use analysis of said in-use signals for each user during an in-use signal interval and updating said priority record of each user on the basis thereof; defining a response transmission right request interval, in which transmitting a response right request signal from each of said responders eligible to respond on its associated channel; parsing said response right request signal for each responder so that the responder can determining whether it has a dominant priority; making available a responder that the analysis indicates has a dominant priority for responding on the intercommunication bus; (6) the priority record of each particular responder is maintained in its own set of (n-1) two-state storage elements, the storage element state being referred to as 0 or 1; Each storage element is associated with a respective channel that is not associated with a particular responder, and the analysis uses the following logic function to determine whether a particular responder has dominant priority for a response. The method according to claim 5, characterized in that it is checked whether: P=T(M_1S_1+1)(M_2S_2+1)...
(M_n_-_1S_n_-_1+1) where T is a 0 or 1 signal from the execution order specified bus channel associated with a specific responder, and M_i is the i-th signal that is not associated with a specific responder. 0 from channel
or a 1 signal, S_i represents a 0 or 1 signal from the ith storage element of a particular responder, and the operation shown is a modulo 2 operation. (7) The value of the state of the two-state memory element is related to the j-th responder, and the value of the two-state memory element in the set associated with the i-th responder is related to the i-th responder. Shij
the value of the two-state storage element in the set associated with the second responder is such that the number of 1's in the priority state record of each responder is different; The method according to claim 6. 8. The method of claim 7, further comprising the step of immediately restarting another transaction if no response request signal is issued during the response request interval. . (9) A response control system for controlling responses by multiple (P) responders to an intercommunication bus providing for the transfer of information between bus users in prescribed transactions, including: having n channels; an execution order specification bus (where n is greater than or equal to P); an access control device associated with each user; a bus system clock that distributes a common clock signal defining time increments to each of said access control devices; an interconnection key associated with each of the access control devices that connects the access control device to the execution priority bus; wherein the access control device includes: a response-ready line connected to the associated user; a transmission line connected to the associated interconnection key; a transmission line connected to the associated interconnection key; There is (n
-1) one monitor line; a control circuit that receives the common clock signal and generates a signal defining a response transmission right request interval; a response transmission right request signal on the transmission line during the response transmission right request interval; a driver circuit responsive to a ready-to-response signal from the associated user on the ready-to-response line to generate a ready-to-response signal; one state of which is designated as 0 and the other state is designated as 1; a priority state storage device comprising (n-1) two-state storage elements respectively associated with each of the monitor lines; generated by the execution order designation logic by performing the following logical operations: , the transmission line and the monitor line and the priority status storage device for generating a priority signal (P) during the response right request interval indicating whether the associated user has a dominant priority or not. Execution order designation logic responsive to signals from; P=T(M_1S_1+1)(M_2S_2+1)...
(M_n_-_1S_n_-_1+1) (In the formula, M
_i represents the signal from the i-th monitor line, S
_i represents the signal from the i-th storage element, T represents the signal from the transmission line, and the operation shown is a modulo-2 operation. ) an access authorization circuit responsive to the priority signal for issuing a response enable signal on the response enable line to enable the associated user to respond on the intercommunication bus; A connection key is each separately associated with one of said execution priority bus channels, and an interconnection between the associated execution priority bus channel and a transmission line of the associated access control device and an unassociated connection key. A response control system comprising: providing an interconnection between a busbar channel and a monitor line of its associated access control device. (10) an access control system for controlling access by a plurality (P) of bus users to an intercommunication bus providing for the transfer of information between said users in prescribed transactions, including: n channels; (where n is greater than or equal to P); an access control device associated with each user; a bus request line connecting each user to its associated access control device; connecting each access control device to its associated user; a bus system clock that distributes a common clock signal defining time increments to each of said access control devices; and a bus system clock that connects said access control device to said execution priority bus; a bound interconnection key; wherein each of the access control devices includes: a transmission line connected to the bound interconnection key; a transmission line connected to the bound interconnection key; (n-1
) book monitor line; a response-ready line connecting to its associated users; a response-enabled line connecting to its associated users; a control circuit for generating a signal defining a usage signal interval; responsive to a bus request signal from the associated user on the bus request line to generate a bus output signal on the transmission line during the contention interval; have sex,
a driver circuit responsive to a response ready signal from the associated user on the response ready line for generating a response transmission right request signal on the transmission line during the response transmission right request interval; Priority state storage device including (n-1) two-state storage elements each associated with each monitor line, one state being designated as 0 and the other state being designated as 1. generating during said contention interval a priority signal (P) indicating whether the associated user has the dominant priority, which is generated by the execution priority logic by performing the following logical operations: To do this, an execution order designation logic responsive to signals from the transmission line and the monitor line and the priority state storage device: P=T(M_1S_1+1)(M_2B_2+1)...
(M_n_-_1S_n_-_1+1) (In the formula, M
_i represents the signal from the i-th monitor line, S
_i represents the signal from the i-th storage element, T represents the signal from the transmission line, and the operation shown is a modulo 2 operation);
responsive to the priority signal for issuing an access grant signal on the grant line during the usage signal interval to enable the associated user to respond on the intercommunication bus; an access granting circuit responsive to the priority signal for issuing a response enable signal on the response enable line; responsive to said access grant signals to generate a signal); responsive to signals on said transmit and monitor lines to review signals stored in said priority state storage during said usage signal interval; an update circuit having; each of said interconnection keys being separately associated with one of said bus channels, and an interconnection between said associated bus channel and said associated access control device transmission line; providing an interconnection between a monitor line of a bus channel and its associated access control device, including initialization means for setting an initial value of the state of the two-state storage element; is j of said channel
the value of the two-state storage element among the i-th one of said access control devices connected to the i-th one of said channel; unequal and such that the number of 1's in the priority state stores of the control units is different; in response to a signal on any of said (n-1) monitor lines for said use signal interval by setting all said (n-1) two-state storage elements to 1; An access control system comprising: responsively setting a corresponding two-state storage element to zero.