JPH0573512A - Multiprocessor system - Google Patents

Abstract

PURPOSE:To speed up the operation of the system by preventing the transfer rate of a system bus from decreasing. CONSTITUTION:The bus request register 11 of a bus monitor device 1 is stored with processor identification numbers PRCID1-PRCID6 that respective processors output as request signals. A processor ready register 12 is stored with ready signals READY1-READY6 indicating communicable states of the respective processors. A bus arbitrating circuit 10 arbitrates the request signals according to the preferential right to use the system bus which is previously set for the processors, the processor identification numbers PRCID1-PRCID6 from the processors which are stored in the bus request register 11, and the ready signals READY1-READY6 from the processors which are stored in the processor ready register 12. The bus arbitrating circuit 10 stores a bus acceptance register 13 with acceptance signals ACCEPT1-ACCEPT6 corresponding to the processors which are allowed to use the system bus according to the arbitration result.

Description

Detailed Description of the Invention

[0001]

TECHNICAL FIELD The present invention relates to a multiprocessor system, and more particularly to a bus control system for a multiprocessor system.

[0002]

2. Description of the Related Art Conventionally, as a bus control method for a multiprocessor system, the priority of use of the system bus is determined for each processor, and the processor having the highest priority of use among the processors that have been requested to use the system bus. There is a method of passing the right to use the system bus.

That is, as shown in FIG. 4, when each processor A to F (not shown) requests the use of a system bus (not shown), a bus request from the bus monitoring device 8 which arbitrates the system bus. Each processor A in the register 81
Request signals REQUEST1 to REQUEST6 from F to F are stored.

The bus arbitration circuit 80 includes processors A to F.
Since the use priority of the system bus is fixed by hardware, the bus arbitration circuit 80 outputs the request signals REQUEST1 to REQUEST6 from the processors A to F stored in the bus request register 81 based on the use priority. Arbitrate. According to the arbitration result, the bus arbitration circuit 80 stores in the bus accept register 82 accept signals ACCEPT1 to ACCEPT6 corresponding to the processors A to F which have granted the right to use the system bus.

For example, if the system bus use priority of each of the processors A to F is determined in the order of processor A> processor B> processor C> processor D> processor E> processor F, each processor A to processor F is determined.
Request signal REQUEST1 to REQUEST6 from F is REQUEST1
＞ REQUEST2 ＞ REQUEST3 ＞ REQUEST4 ＞ REQUEST5 ＞ REQUEST6
That is the priority order.

If the request signal REQUEST1 and the request signal REQUEST5 are simultaneously stored in the bus request register 81, the bus arbitration circuit 80 determines the priority order of the request signal REQUEST1 and the request signal REQUEST5. In this case, the bus arbitration circuit 80 determines that the request signal REQUEST1 has priority over the request signal REQUEST5, and in order to give the processor A that has output the request signal REQUEST1 the right to use the system bus, the bus arbitration circuit 80 sends an accept signal ACCEPT1 corresponding to the processor A. It is stored in the bus accept register 82.

The processor A uses the bus accept register 8
When receiving the accept signal ACCEPT1 from 2, it communicates with the processor of the communication partner. At this time, if the processor of the communication partner is performing internal processing or is communicating with an external peripheral device, the processor of the communication partner cannot immediately respond to the communication request from the processor A. .. In this case, the processor A keeps occupying the system bus and waits until the processor of the communication partner becomes in the communicable state.

In such a conventional bus control method, the right to use the system bus is handed over to the processor having the higher right to use, so that the communication partner of the processor that has obtained the right to use the system bus must be in the communicable state. There is a problem that the system bus is occupied by the processor until the communication partner is in a communicable state, and the transfer rate of the system bus is deteriorated, which hinders the speeding up of the system.

[0009]

SUMMARY OF THE INVENTION The present invention has been made to eliminate the above-mentioned problems of the prior art, and is capable of preventing the transfer rate of the system bus from deteriorating and increasing the speed of the system. The purpose is to provide the system.

[0010]

A multiprocessor system according to the present invention is a multiprocessor system composed of a plurality of processors each connected by a system bus, and is provided in each of the plurality of processors, and is connected to its own device via the system bus. A first sending means for sending connection information indicating whether connection with another device is possible or not, and the first sending means provided in each of the plurality of processors, when requesting a connection with another device via the system bus. Second sending means for sending identification information for specifying another device, the connection information from the first sending means, the identification information from the second sending means, and the plurality of processors set in advance Means for permitting access to the system bus in accordance with the priority of the system bus.

[0011]

DESCRIPTION OF THE PREFERRED EMBODIMENTS Next, the present invention will be described with reference to the drawings.

FIG. 1 is a block diagram showing the system configuration of an embodiment of the present invention. In the figure, the bus monitoring device 1 is connected to each of the processors 2 to 7 via a system bus 100, and arbitrates the right to use the system bus 100 for each of the processors 2 to 7.

Ready signals sending circuits 2a, 3a, 4a, 5a, 6a, 7a for sending ready signals indicating that the device itself is in a communicable state are provided to the processors 2 to 7, respectively.
Processor identification number sending circuits 2b, 3b, 4b, 5b, 6b, 7 for sending the identification number of the communication partner processor as a request signal when the system bus 100 is used.
b and are provided.

FIG. 2 is a block diagram showing the configuration of the bus monitoring device 1 of FIG. In the figure, in the bus request register 11 of the bus monitoring device 1, processor identification number sending circuits 2b, 3b, 4b, 5b, 6 of the processors 2-7 are provided.
The processor identification numbers PRCID1 to PRCID6 output as request signals from b and 7b are stored. Further, ready signals READY1 to READY6 output from the ready signal sending circuits 2a, 3a, 4a, 5a, 6a and 7a of the processors 2 to 7 to the processor ready register 12 and indicating the communicable states of the processors 2 to 7, respectively. Is stored.

The bus arbitration circuit 10 includes processors 2 to 7 respectively.
The use priority of the system bus 100 is fixed by hardware, and the bus arbitration circuit 10 uses the use priority and each of the processors 2 to 7 stored in the bus request register 11.
From the processor identification numbers PRCID1 to PRCID6 and the processors 2 to 7 stored in the processor ready register 12
The arbitration of the request signal is performed based on the ready signals READY1 to READY6 from. The bus arbitration circuit 10 accepts signals ACCEPT1 to ACCEPT corresponding to the processors 2 to 7 that have granted the right to use the system bus 100 according to the arbitration result.
6 is stored in the bus accept register 13.

For example, if the use priority of the system bus 100 of each of the processors 2 to 7 is determined in the order of processor 2> processor 3> processor 4> processor 5> processor 6> processor 7, then each processor 2 to 7 is determined. Processor identification numbers PRCID1 to PRCID6 output as request signals from PRCID1>PRCID2>PRCID3> PR
The priority order is CID4>PRCID5> PRCID6.

Now, the ready signal sending circuits 2a, 3a and 4 of the processors 2 to 7 are added to the processor ready register 12.
Ready signal READY1 ~ from all a, 5a, 6a, 7a
With the READY6 stored, the processor identification numbers PRCID1 and PRCID5 from the processor identification number sending circuits 2b and 6b of the processors 2 and 6 are stored in the bus request register 11.
, The bus arbitration circuit 10 arbitrates the request signal based on the use priority of the system bus 100 of the processors 2 and 6 and the communicable state of the processor with which the processors 2 and 6 are communicating. ..

In this case, since all the processors 2 to 7 are in the communicable state, the bus arbitration circuit 10 sends the accept signal AC to the bus accept register 13 in order to give the processor 2 permission to use the system bus 100.
Stores CEPT1. Therefore, when the processor 2 receives the accept signal ACCEPT1 from the bus accept register 13, the processor 2 communicates with the processor of the communication partner.

Next, the processor identification number sending circuit 2b of the processor 2 outputs a processor identification number PRCID1 indicating the identification number of the processor 5 as a request signal,
At the same time, the processor identification number sending circuit 6b of the processor 6
When the processor identification number PRCID5 indicating the identification number of the processor 3 is output as a request signal from the processor, the processor identification numbers PRCID1 and PRCID5 are simultaneously stored in the bus request register 11.

At this time, the processor ready register 12
Assuming that the ready signal READY4 from the ready signal sending circuit 5a of the processor 5 is not stored in and the ready signal READY2 from the ready signal sending circuit 3a of the processor 3 is stored in the bus arbitration circuit 10, the bus arbitration circuit 10 has a higher priority of use. It is determined that the processor 5 as the communication partner of the processor 2 is not in the communicable state, and the processor 6 having a lower use priority is allowed to use the system bus 100. That is, the bus arbitration circuit 10 stores the accept signal ACCEPT5 to the processor 6 in the bus accept register 13. Therefore, when the processor 6 receives the accept signal ACCEPT5 from the bus accept register 13, the processor 6 communicates with the processor 3 of the communication partner.

FIG. 3 is a block diagram showing the configuration of a bus monitoring device according to another embodiment of the present invention. In the figure, another embodiment of the present invention has the same configuration as that of the embodiment of the present invention shown in FIG. 2 except that a processor busy register 14 is provided in place of the processor ready register 12, and the same components are provided. Are given the same reference numerals. The operation of those same components is the same as that of the embodiment of the present invention.
In another embodiment of the present invention, the ready signal sending circuit 2a,
Instead of 3a, 4a, 5a, 6a, 7a, a busy signal sending circuit is provided in each processor 2-7.

Processor identification numbers PRCID1 to PRCID output from the processor identification number sending circuits 2b, 3b, 4b, 5b, 6b and 7b of the processors 2 to 7 to the bus request register 11 of the bus monitoring device 1 as request signals.
CID6 is stored. Also, processor busy register 1
Busy signals BUSY1 to BUSY6, which are output from the busy signal sending circuits of the processors 2 to 7 and indicate the communication disabled state of the processors 2 to 7, are stored in the block 4.

The bus arbitration circuit 10 includes processors 2 to 7 respectively.
The use priority of the system bus 100 is fixed by hardware, and the bus arbitration circuit 10 uses the use priority and each of the processors 2 to 7 stored in the bus request register 11.
From the processor identification numbers PRCID1 to PRCID6 and the processors 2 to 7 stored in the processor busy register 14.
The request signal is arbitrated based on the busy signals BUSY1 to BUSY6 from. The bus arbitration circuit 10 accepts signals ACCEPT1 to ACCEPT corresponding to the processors 2 to 7 which have granted the right to use the system bus 100 according to the arbitration result.
6 is stored in the bus accept register 13.

For example, if the use priority of the system bus 100 of each of the processors 2 to 7 is determined in the order of processor 2> processor 3> processor 4> processor 5> processor 6> processor 7, then each processor 2 to 7 is determined. Processor identification numbers PRCID1 to PRCID6 output as request signals from PRCID1>PRCID2>PRCID3> PR
The priority order is CID4>PRCID5> PRCID6.

Now, with the busy signals BUSY1 to BUSY6 from all the busy signal sending circuits of the processors 2 to 7 stored in the processor busy register 14, the processor identification number sending circuits 2b and 6b of the processors 2 and 6 receive the signals. When the processor identification numbers PRCID1 and PRCID5 are simultaneously stored in the bus request register 11, the bus arbitration circuit 1
0 arbitrates the request signal based on the use priority of the system bus 100 of the processors 2 and 6 and the communication disabled state of the processor of the communication partner of the processors 2 and 6.

In this case, since all the processors 2 to 7 are in the communication disabled state, the bus arbitration circuit 10 sends the accept signal AC to the bus accept register 13 in order to give the processor 2 permission to use the system bus 100.
Stores CEPT1. Therefore, when the processor 2 receives the accept signal ACCEPT1 from the bus accept register 13, the processor 2 communicates with the communication partner processor when the processor becomes ready to communicate.

Next, the processor identification number sending circuit 2b of the processor 2 outputs a processor identification number PRCID1 indicating the identification number of the processor 5 as a request signal,
At the same time, the processor identification number sending circuit 6b of the processor 6
When the processor identification number PRCID5 indicating the identification number of the processor 3 is output as a request signal from the processor, the processor identification numbers PRCID1 and PRCID5 are simultaneously stored in the bus request register 11.

At this time, the processor busy register 14
The busy signal from the busy signal sending circuit of the processor 5
If BUSY4 is stored and the busy signal BUSY2 from the busy signal transmission circuit of the processor 3 is not stored, the bus arbitration circuit 10 disables the communication partner processor 5 of the processor 2 having the higher use priority. Therefore, the accept signal ACCEPT5 is stored in the bus accept register 13 in order to give permission to use the system bus 100 to the processor 6 whose use priority is lower.
Therefore, when the processor 6 receives the accept signal ACCEPT5 from the bus accept register 13, the processor 6 communicates with the processor 3 of the communication partner.

As described above, the communication state indicating whether communication is possible or not in the communication destination processor of each processor 2 to 7 and the system bus of each processor 2 to 7 set in advance
The bus monitoring device 1 determines the processor that passes the usage right according to the usage right of 100
100 can be used efficiently. Therefore, the transfer rate of the system bus 100 can be prevented from deteriorating, and the system speed can be increased.

[0030]

As described above, according to the present invention, it is judged by the bus monitoring device whether the processor outputting the communication request and the processor of the communication partner can be connected, and the judgment result and each By arbitrating the bus use right according to the priority of the processor, it is possible to prevent the transfer rate of the system bus from being deteriorated and to speed up the system.

[Brief description of drawings]

FIG. 1 is a block diagram showing a system configuration of an embodiment of the present invention.

FIG. 2 is a block diagram showing a configuration of a bus monitoring device shown in FIG.

FIG. 3 is a block diagram showing a configuration of a bus monitoring device according to another embodiment of the present invention.

FIG. 4 is a block diagram showing a configuration of a conventional bus monitoring device.

[Explanation of symbols]

1 Bus monitoring device 2 to 7 processor 2a, 3a, 4a, 5a, 6a, 7a Ready signal sending circuit 2b, 3b, 4b, 5b, 6b, 7b Processor identification number sending circuit 10 Bus arbitration circuit 11 Bus request register 12 Processor ready Register 13 Bus accept register 14 Processor busy register

Claims (1)

[Claims] 1. A multiprocessor system comprising a plurality of processors each connected by a system bus, wherein each of the plurality of processors is provided with a connection between its own device and another device via the system bus. First transmitting means for transmitting connection information indicating whether or not it is impossible, and identification information that is provided in each of the plurality of processors and that identifies the other device when requesting connection with the other device via the system bus. The second sending means for sending, the connection information from the first sending means, the identification information from the second sending means, and a preset priority of each of the plurality of processors A multiprocessor system comprising means for permitting access to a system bus.