JPS63296159A - Microcomputer system - Google Patents

Abstract

PURPOSE:To facilitate the design of software and to reduce load on the software, by delaying an access signal outputted from a microprocessor to an input/ output equipment in a hardware way. CONSTITUTION:A delay circuit 8 outputs an I/O access signal ASA or ASB to respective signal line 80A or 80B by delaying it corresponding to the operating speed of I/O device 21-24 in two stages, for example, corresponding to the operating speed of I/O devices 21 and 22 which belong to a fast I/O device group 2A and I/O devices 23 and 24 which belong to a slow I/O device group 2B. Therefore, even when the microprocessor outputs a port address to select the input/output equipment and an access signal to operate the input/output equipment successively, they are supplied to the input/output equipment by delaying the access signal by a time equivalent to the recovery time of the input/output equipment. In other words, the guarantee of the delay time of an operation possible to perform the actual transmission/reception of the data after a time when a select signal reaches the input/output equipment is performed in the hardware way. In such a way, it is possible to make a processing by the software unnecessary, and to reduce the load on the software.

Description

DETAILED DESCRIPTION OF THE INVENTION [Field of Industrial Application] The present invention relates to a microcomputer system, and more particularly to a microcomputer system in which a method for accessing input/output devices by a microprocessor is improved.

[Conventional technology]

Figure 2 shows, for example, risBc 386/100ES
5INGLI! BOARD C0MPUTl! RUS
T! R'S GUIDf! (Intel, 1986)
FIG. 2 is a block diagram of the hardware configuration of the microprocessor and input/output devices of the microcomputer system described in J.

In the figure, 1 is a microprocessor (hereinafter referred to as CPυ), and 2 is an input/output device (hereinafter referred to as IO device) controlled by this CPUI. The 10 devices 2 are equipped with a chip select a terminal 2S and a control signal terminal 2C.

3 in the figure operates by decoding the port address given from the CPU via the address bus 4;
In other words, ■0 device 2 where data transmission and reception should be controlled
This is an address decoder that generates 10 select signals SS for selecting.

Note that the 10 select signal SS generated by the address decoder 3 is applied to the chip select terminal 2S of the ■0 device 2 via the ■00 select signal line 5.

6 is a data bus for transmitting data between the CPUI and the 10 devices 2;

Reference numeral 7 denotes an IO access signal line for applying an IO access signal As outputted from the CPU 1 to operate the 10 devices 2 to the control signal terminal 2C of the 10 devices 2.

The CP of such a conventional microcomputer system
The operation when the UI accesses the ■0 device 2 and transfers data is as follows.

First, the CPIJI provides the address decoder 3 via the address bus 4 with a port address <address specifying the TO device. The address decoder 3 decodes the applied boat address to generate a 00 select signal SS, which is applied to the chip select terminal 2S of the 10 devices 2 via the IO select signal line 5.

Next, the CPU gives the 10 access signal ^S to the control signal terminal 2C of the IO device 2 via the 00 access signal line 7, and transmits the data to the 10 device 2 via the data bus 6.

As a result of the above, 10 devices 2 are activated and CPt
Data transmission from 1l to 10 devices 2 takes place.

[Problem that the invention seeks to solve]

By the way, when accessing ■0 device 2 by CPIII as described above, (:PUl operating speed and IO
The operating speed of device 2 is different, more specifically TO
Generally, the operating speed of the device 2 is slower than that of the CPU 1.

Therefore, it is necessary to adjust the timing when transmitting and receiving data between the two. More specifically, the CPUI
IO device 2 before accessing IO device 2
must have already completed preparations for sending and receiving data.

In other words, at the time the ■00 access signal AS output from the CPUI is input to the control signal terminal 2C of the 10 device 2, the ■0 device 2 must already be ready to send and receive data. be.

This preparation time for the IO device 2 is called one hour of recovery. In conventional microcomputer systems such as the above-mentioned system, the timing at which the IO access signal AS is given is delayed from the timing at which the 10 select signal SS is given to the IO device 2 by software processing. Then C
One hour of recovery is guaranteed by outputting 10 access signals with a slight delay after Pt1l outputs the boat address.

For this reason, in conventional microcomputer systems, C
If the software processing in the PU 1 becomes complicated, and if a plurality of 10 devices are provided and each operating speed is different, it will be necessary to perform software processing according to the operating speed of each of the 10 devices. Therefore, the problem arises that the software design becomes extremely complicated and the burden on the software becomes large.

The present invention was made in view of these circumstances, and
Due to the difference in operating speed between the microprocessor and input/output equipment, by guaranteeing one-hour recovery time with hardware, multiple input/outputs with different operating speeds can be handled.
! To provide a microcomputer system capable of guaranteeing recovery time of each input/output device within one hour without the intervention of software even when the computer is equipped with a microcomputer system including 5.

[Means for solving problems]

The microcomputer system of the present invention employs a configuration in which the access signal output from the microprocessor to the input/output device is delayed by hardware on the path from the microprocessor to the input/output device, and When a plurality of input/output devices having different speeds are provided, each access signal is delayed according to the operating speed of each input/output device.

[Effect]

In the microcomputer system of the present invention, even if the microprocessor successively outputs a boat address for selecting an input/output device and an access signal for operating an input/output device, the access signal is 3
The signal is delayed by a time corresponding to one hour for one device to recover and is applied to the input/output devices.

[Embodiments of the invention]

DESCRIPTION OF THE PREFERRED EMBODIMENTS The present invention will be described in detail below based on drawings showing embodiments thereof.

FIG. 1 is a block diagram showing the hardware configuration around a microprocessor and input/output devices of a microcomputer system according to the present invention. In addition, in FIG. 1, the same reference numerals are given to the same or corresponding parts as in FIG. 2 used to explain the above-mentioned conventional technology.

In the figure, 1 is a microprocessor (hereinafter referred to as CPU), and 21, 22, 23, and 24 are input/output devices (hereinafter referred to as IOOR chair) controlled by the CPU 1, and in this embodiment, the IO device 21 and 22 is high speed■0
0 device 2A, and 10 devices 23 and 24 constitute low speed 00 device 2B. Each of the ■0 devices 21, 22, 23, and 24 has chip select terminals 21S, 22S, 23S, and 2, respectively.
43 and control signal terminal 21C.

22C, 23C, and 24C are provided.

3 in the figure is an address decoder that generates one of the 0 select signals SS1 to SS4 for selecting the IO device to be operated by decoding the port address given from the CPIII via the address bus 4. be.

Note that the IO select signal 5Sl (or SS2.SS3.5S4) generated by the address decoder 3 is the IO
■ Chip select terminal 21S (or 22S, 23S, 24S) of 0 device 21 (or 22.23.24) via select signal line 51 (or 52.53.54)
) as well as the IO select signal S31. SS2
are connected to the first switching terminal 8A of the delay circuit 8 and one input terminal of the ND gate 9^ (to be described later) via the OR gate IOA, and also to the 0 select signal SS3. SS4 is OR game 1
-10B to the second switching terminal 8B of the delay circuit 8 and one input terminal of the AND gate 1-98 for f&if.

6 is cpυ1 and each 10 devices 21, 22.23.24
This is a data bus for transmitting data between.

7 is ■0 devices 21, 22, 23.24 in groups,
That is, it is a TO access signal line for applying a 0 access signal ASA or ^3B from the CPUI to the delay circuit 8 for operating the high speed IO device group 2A or the low speed IO device group 2B.

The delay circuit 8 transmits the ■0 access signal ^SA or ASB given from the CPUI to the respective ■0 devices 21, 2.
According to the operating speed of 2°23.24, high speed T is used in this implementation.

10 devices 21 and 22 belonging to device group 28 and 10 devices 23 and 2 belonging to low-speed IO device group 2B
The signals are delayed in two stages corresponding to the operating speed of 4 and output to the respective signal lines 80^ and 80B.

More specifically, fast! When the 0 select signal SS1 or SS2 applied to the 00 device 2^ becomes high level, it is sent to the first gate of the delay circuit 8 via the OR gate IOA.
The signal delay time of the delay circuit 8 is switched to a relatively small first delay time, and the IO select signal S is applied to the low-speed 10 device group 2B.
When S3 or SS4 becomes high level, OR gate 10
This signal is applied to the second switching terminal 8B of the delay circuit 8 via the signal line B, and the signal delay time of the delay circuit 8 is switched to a relatively larger second delay time.

Note that the signal line 80A is connected to the control signal terminals 21C and 22C of the ■0 devices 21 and 22 via the AND game) 9A.
Further, the signal line 80B is connected to the control signal terminals 23C and 24C of the IO devices 23 and 24 through the AND gate 9B, and the output of the OR gate IOA is connected to the other input terminal of the AND gate 9A as described above. , also AN
D game) 9B's other input terminals are as described above <OR game)
An output of 10B is provided respectively.

The operation when CPt1l accesses To device 2 and sends and receives data in the microcomputer system of the present invention is as follows.

First, CPt1l is the port address (10 devices 21
24) is given to the address decoder 3 via the address bus 4. As a result, the address decoder 3 outputs the 10 select signal 5SI (or
SS2, SS3, 534) and use it as IO
The chip select terminal 21S (or 225, 235, 245) of the ■0 device 21 (or 22, 23, 24) is connected to the
).

Next, CPt1l accesses the IO via the IO access signal line 7.
The access signal ASA (or ASB) is outputted and applied to the delay circuit 8, and data is outputted via the data bus 6.

At this time, for example, if the port address is specified [
0 device is fast ■ Any 10 to 00 device 2
In the case of devices 21 and 22, a high level signal is applied to the first switching terminal 8A of the delay circuit 8 via the OR gate 10^, so that the delay time of the signal by the delay circuit 8 is relatively small. The delay time is switched to . Therefore, the 10 access signals ASA output from the CPUI are delayed by the relatively small first delay time, and the signal line 80 is
A, Control signal terminal 21 of both 10 devices 21 and 22 of high-speed IO device group 2A via AND game 1-9A
C and 22C.

On the other hand, for example, it is specified by the port address! 0
If the device is one of the ■0 devices 23 and 24 of the low-speed IO device group 2B, a high level signal is given to the second switching terminal 8B of the delay circuit 8 via the OR gate 10B. The delay time of the signal due to the delay time is switched to a second delay time which is relatively large. Therefore, the 10 access signal ASB outputted from CPt1l is delayed by a relatively large second delay time, and the signal line 80
B, AND game) 9[1 through the control signal terminal 23 of both IO devices 23 and 24 of the low-speed IO device group 2B
C and 24C.

In this way, CPU1 selects 10 select signals SSI and IO
When the access signal ASA is output, the IO device 21 of the high-speed 10 device group 2A is accessed, and when the ■00 select signal SS2 and the 10 access signal ASA are output, the IO device 22 of the high-speed ■00 device 2A is accessed. , when the 10 select signal SS3 and the IO access signal ASB are output, the 10 devices 23 of the low-speed 10 device group 2B are accessed, and the IO select signal S
When S4 and ■0 access signal ASB are output, 10 devices 24 of low-speed ■00 devices 2B are accessed.

As described above, data is transmitted from the CPU 1 to any one of the IO and f devices 21 to 24.

In this way, the time from when the ■00 select signals SSI to SS4 arrive at each ■0 device 21, 22, 23.24 until the 10 access signal ASA or ASB delayed by the delay circuit 8 arrives is determined by the recovery time. It's time.

Note that in the above embodiment, a plurality of 10 devices are divided into two groups, a high-speed 10-device group and a low-speed 10-device group, and the IO access signal is delayed in two stages by a delay circuit depending on the IO device to be accessed. However, if there is only one IO device or if there are multiple IO devices but their operating speeds are between 1 and 2, the delay time may of course be one step, and if the operating speeds of multiple RO devices are three or more steps. Of course, in different cases, it is possible to subdivide the delay time of the delay circuit into three or more stages.

〔Effect of the invention〕

As described above, according to the present invention, when an input/output device is accessed by a microprocessor, the input/output device is covered for one hour, that is, from the time when a select signal reaches the input/output device to when actual data transmission/reception becomes possible. Since the delay time of the operation is guaranteed by hardware, the conventional software processing is unnecessary, and the burden on the software is reduced.

[Brief explanation of the drawing]

FIG. 1 shows a microprocessor and input/output tJl! of a microcomputer system according to the present invention. Figure 2 is a block diagram showing the hardware configuration around the microprocessor and input/output devices of a conventional microcomputer system. 1...CPU 2A...High speed 10 device group
2B...Low speed ■00 device 8...Delay circuit 21.22, 23.24...■0 device Note that the same reference numerals in each figure indicate the same or corresponding parts.

Claims (1)

[Scope of Claims] 1. A microcomputer equipped with a microprocessor and an input/output device that is specified as a data transmission/reception target by a select signal outputted by the microprocessor and whose data transmission/reception is executed by an access signal. In the system, in order to eliminate the delay in the operation of the input/output equipment from the time when the select signal output from the microprocessor arrives until data transmission/reception becomes possible,
A microcomputer system comprising a delay circuit that delays arrival of the access signal to the input/output device. 2. A microcomputer system comprising a microprocessor and a plurality of input/output devices that are designated as data transmission/reception targets by a select signal output by the microprocessor and whose data transmission/reception is executed by an access signal, In order to eliminate the delay in the operation of each of the input/output devices from the time when the select signal output from the microprocessor arrives until data transmission/reception becomes possible, the arrival of the access signal to the plurality of input/output devices is A microcomputer system characterized by being equipped with a delay circuit that delays by different times.