JPS58159282A - Data output control circuit - Google Patents

Abstract

PURPOSE:To avoid the effect of switching noise of a driver, by latching an address inputted to a collation circuit during the data output period based on the coincidence of addresses. CONSTITUTION:A strobe outputted from the collation circuit 2 in response to the coincidence of addresses is an enable signal DEN via an AND gate 4 and a data of a register 3 is outputted via a driver 5. A latch circuit 6 responds to the driver during the output period of the driver 5 and the address from a receiver 1 is latched to the circuit 6 and not inputted to the circuit 2. Thus, noise due to the power supply fluctuation attended with the switching of the driver 5 and the coupling capacitance change does not give any change on the circuit 2.

Description

DETAILED DESCRIPTION OF THE INVENTION The present invention relates to a control circuit that sends data onto a data bus in response to a specific address output onto an address bus.

Conventionally, there has been a control circuit of this type as shown in FIG. In Figure 1, (1) is the address bus (]a)
A receiver (21i
A verification circuit %() receives the upper address signal ADSU from the receiver (1) via the address bus (lb) and energizes the address match signal ADIN at a predetermined time.
3) is connected to the receiver (1) via the address bus (IC)
(4) A register that receives the lower address signal AL)SL from and reads data from it, and (4) generates an enable signal 1) EN by ANDing the address match signal AI)IN and the strobe signal STR. (5) transfers data 1) AT& of register (3) to data bus (5a) in response to enable signal DEN.
).

To explain the operation, the address signal AD8 is
1) to the verification circuit (2), where it is verified against its own address. As a result, when the own address is output, the address match signal ADIN goes high, the strobe signal STR opens the AND gate (4), and the AND gate (4) outputs the enable signal DEN of the driver (5). Set to high and vi.

On the other hand, the register (3) has its address specified by the address signal AD8U, and outputs, ie, reads, the data DATA by the strobe signal STR. This (5a)
will be sent to.

By the way, when the driver (5) is enabled by the enable signal DEN, switching noise is led to the address bus (la) via an unillustrated power supply (EU path) or by electrical floating coupling, and the verification circuit This disturbs the matching in (2) and causes it to become a mismatch. When this switching noise disappears, the matching circuit (2) detects address matching again and sets the enable signal DEN to high "lo". , switching noise occurs again, and the following ij ■ is repeated, resulting in data loss.
The data on the bus (5a) will be affected by switching noise.

Conventional data output side diagonal circuits have a configuration in which noise generated on the data bus is superimposed on the address signal on the address path, so the data on the data bus is not affected by switching noise. However, there was a drawback in that the correct data could not be transferred to the other party connected to the data bus.

This invention was made for the purpose of eliminating the drawbacks of the conventional ones such as the one in which the address signal input to the verification circuit is latched during the data output period by the address match signal of the verification circuit. This provides a single circuit on the data output side that can prevent data on the data bus from being affected by switching noise of the driver.

An embodiment of the present invention will be explained below with reference to the block diagram of FIG. 2. In FIG. 2, the same parts as in FIG. Latch the direct IT+ human input signal that becomes
This is a latch circuit (such as 74L875 in a general-purpose IC) that outputs the contents of this latch and does not change the output signal even if the human input signal changes. do.

Figure 2 shows the above latch circuit added to Figure 1.
This is the configuration.

FIG. 3 is a time chart for explaining the operation of the circuit shown in FIG. 2 in comparison with the case of FIG. address signal (
address signal At)S via la)
and the latch circuit (6).

At this point (time tl), the strobe signal STR
is on the unintentional side, and since the E input of the latch circuit (6) is unintentional, the latch circuit (6) #'i input is output as is. From this, the address signal At)SU is sent to the matching circuit (2). Time 1. If the address signal kDsUO is the address of the circuit, that is, the self address, then the address match signal AL)IN is the matching circuit (2)
It is output from Thereafter, at time t, the strobe signal STR is generated and the register (3) receives the address signal A.
L) The data at the address 7L specified by the contents of SL is output, and an enable signal D) UN is output.

By the enable signal L)EN, (1) the driver (5) sends the data IJATA output from the register (3) to the data bus (5a).

(2) The launch circuit (6) is the direct spinning address signal A.
Latch DS and output the contents of this latch.

(Afterwards, while the IJEN signal is significant, the latched contents are output even if the input address signal changes.) Switching noise occurs when the driver (5) outputs data to the data bus (5a). is the address signal AI
JS, but is not affected by the output of the latch circuit (6), the address AI)SL ADSU is stable, and the address match signal AI)IN and enable signal DhiN
, the output data DATA of the register (3) are both stable, and the data DATA output to the data bus (5a) is stable.

As described above, according to the present invention, in the first circuit on the data output side configured to open the driver that sends data with an address matching number, while the driver is open, the address signal is latched, Since changes in the address signal are not accepted, the address signal is affected by the switching noise that occurs when the driver is opened, making the data on the t1 data bus stable and unaffected by switching noise. be able to.

[Brief explanation of drawings]

FIG. 1 is a circuit diagram of a conventional data output control circuit, FIG. 2 is a circuit diagram showing an embodiment of the data output control k1 circuit according to the present invention, and FIG. 3 is a circuit diagram of a conventional data output control circuit. It is a time chart explaining the operation. In the figure, (1) is the receiver, (2) is the verification IJ13
] path, (3) is a register, (4) is an AND gate, (
51rJ driver, (6) is a latch circuit. In addition, in the figure, the numerals ``-'' indicate the same parts. Agent Makoto Tameno- Figure 1 Figure 2 1-J Q l-+
\+3+ri fear ρ

Claims (1)

[Claims] A verification circuit that compares the input address signal with a preset self-address to detect a match, a driver that sends data by the output of this verification circuit, and a driver that sends data to the verification circuit during the output period of this driver. A data output side circuit with a latch circuit that launches an address signal input manually.