JPS5926415Y2 - Digital interface circuit - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION The present invention relates to a circuit for implementing the IEEE 5td488.1975 standard for digital busbars and their interfaces.

The conventional circuit is shown in detail in the above standard, but the main point is that in addition to using 8-bit parallel data lines,
The ink face is controlled by signals from the book's dedicated line to transmit digital data.

FIG. 1 is a diagram explaining this part.

In the figure, eight data lines DIOI, 2.・・・・・・
, 8 are collectively represented by symbol A, three handshake lines DAV, NDAC, and NRFD are collectively represented by symbol B, and five control lines SRQ, IFC, REN, EOI, AT.
N is collectively represented by the symbol C.

Data line A is used by switching between data mode and command mode.

Figure 2 shows the distinction, and shows the ATN in control line C.
It is distinguished from command mode D if the signal is at the L level, and data mode E if the signal is at the H level.

The signal sent on data line A is used for internal communication between interfaces in command mode D, and is used for data transmission between target devices in data mode E.

Data transmission is confirmed by a so-called three-wire handshake using the /'% handshake line B.

FIG. 3 is a diagram explaining this operation.

In the figure, when the receiving side of the data is ready to accept it, the NR
Raise FD to H level.

On the data transmitting side, after placing data on the data line A in advance, it continues to monitor NRFD, and when it reaches the H level, DAV, which had been kept at the H level, is lowered to the L level.

When the receiving side of the device detects that DAV goes to L level, it accepts data from data line A, and when that is completed, it sets NDAC to H level.

When the data sending side detects this, it prepares the next data, waits until the receiving side is ready, and then enters the next cycle.

In order to decode and execute the functions, data, and instructions outlined above, devices that combine a large number of digital logic circuits have been put into practical use.

Although it is convenient to use a microcomputer to decipher and operate more complex instructions and data, the operating time of each part of the interface section is standardized, and it is difficult to use a normal microcomputer. The disadvantage was that the required time was significantly shorter than that of the evening operation, and a large number of external circuits had to be added.

The object of this invention is to provide a digital interface circuit which does not have the drawbacks mentioned above.

The feature of this invention is that the interface circuit described above is
A desired interface circuit can be realized by simply providing a simple external circuit to a microcomputer of normal speed.

In other words, if we examine the current standard in detail, there are some parts that require a response faster than several tens of microseconds, which is the response speed of a microcomputer program. It was found that adding the required interface behavior was obtained.

An embodiment of the present invention will be described in detail below with reference to FIG.

In the figure, command mode d ends, and
When TN changes from the L level to the H level, the microcomputer 1 detects this and responds, but the speed cannot meet the standard of 200 ns or less.

Therefore, the ATN signal is applied to the flip-flop 2, and the transistor 3 temporarily maintains NRFD at L level.

When NRFD is at L level, the bandshake operation does not proceed even if the ATN switches to data mode, so no data transmission is performed.

Microcomputer 1 is later than this, and ATN becomes H.
level, and in response, the NRFD
Latch 4 outputs the H level signal of NDAV and the L level signal of NDAV.
Output via .

This resets flip-flop 2 and transistor 3 opens NRFD.

Component 5 in the figure is a latch that outputs signal bits other than those included in the output latch 4, 6 is a human gate, 7 is a standard digital bus dedicated bus transceiver, and 18 is a decoder that decodes address instructions from the microprocessor. It is.

As explained above, according to the present invention, an interface with a standard digital bus having abundant functions can be obtained using a relatively slow response microcomputer without adding a complicated digital circuit.

Further, similar effects can be obtained by using the NDAC line instead of the NRFD line based on the same principle as described above.

[Brief explanation of drawings]

Fig. 1 is an exploded view of the data line, bandshake line, and control line of a standard digital bus, Fig. 2 is a diagram showing a method for time-division use of the digital bus, and Fig. 3 is the principle of 3-line bandshake. FIG. 4 is a wiring diagram of the interface circuit according to the present invention. A: data line, B: band shake line, C: control line, 1: microcomputer, 2: flip-flop ,3・
...Transistor, 4...Output latch,
5... Output latch, 6... Input gate, 7... Dedicated path transceiver 8...
・Tecoder.

Claims (1)

[Scope of utility model registration request] In the standard digital bus interface circuit shown in IEEE-5td 488, 1975, when the input signal is decoded and controlled using a computer,
A flip-flop or latch that operates according to changes in the ATN signal is provided, and this is connected to the NRFD line or ND line.
A circuit connected to an AC line is provided to compensate for slow response of the computer by holding the NRFD line or the NDAC line in a pinch until the computer's operation catches up. digital interface circuit.