JPH049350B2 - - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION (Technical Field) The present invention relates to an interrupt synchronization method applied to an electronic computer system consisting of a minicomputer, a microcomputer, and a microcomputer peripheral circuit.

(Background Art) In an electronic computer system in which a minicomputer controls a microcomputer device, data exchange between the minicomputer and the microcomputer device is performed by the following method.
The case where a microcomputer device is used as an input device will be described below.

When the microcomputer device obtains the data to be sent to the minicomputer, it sets an interrupt flip-flop (hereinafter referred to as interrupt FF) within the microcomputer device, and issues an asynchronous interrupt to the minicomputer to notify it of the existence of the data. The minicomputer either reads data in response to an interrupt, or asynchronously reads data from the peripheral circuits of the microcomputer device. Data is exchanged using the above method.

By the way, in the system, if the time when the microcomputer sets the interrupt FF to the minicomputer and the time when the minicomputer issues a data request signal to the microcomputer overlap, an interrupt is generated while the data request tag line is active.
The state of FF may change. If data related to the interrupt status is sent to the minicomputer in response to a data request signal in such a case, there will be a discrepancy between the information obtained from the data and the interrupt information in the minicomputer, making it impossible to make a decision. In some cases, it may not be possible to continue processing.

In order to prevent such a situation, conventionally, the circuit shown in Fig. 1 has been used to synchronize the minicomputer and the microcomputer.
In FIG. 1, 1 is a microcomputer device, 2 is a minicomputer, 3 is a microcomputer, 4 is a peripheral circuit accessed from the microcomputer and the minicomputer, 5 is a microcomputer bus,
6 is a common bus, 7 is a minicomputer bus, 8 is a gate of the microcomputer bus 5 that opens when 1 is input to the gate terminal e, 9 is a gate of the minicomputer bus 7 that opens when 1 is input to the gate terminal f, and 10 is a gate of the minicomputer bus 7 that opens when 1 is input to the gate terminal f. A flip-flop for microcomputer synchronization is set when 1 is input to the set terminal g, and reset when 1 is input to the reset terminal h; 11 is a set terminal i;
It is set when 1 is input to
12 is a not circuit, 13 is an AND circuit, a is an interrupt output terminal that informs the minicomputer that the microcomputer has obtained data, and b is an interrupt input. terminals, c is an interrupt reset terminal, d is a data request signal terminal, e is a gate terminal of the microcomputer bus gate 8,
f is the gate terminal of the mini-combbus gate 9, g is the set terminal of the synchronizing flip-flop 10, h is the reset terminal, i is the set terminal of the interrupt flip-flop, and j is the reset terminal.

When the minicomputer 2 does not request data, 0 is output from the data request signal terminal d. Since 0 is input to the gate terminal f of the mini-computer bus gate 9, the mini-combus gate 9 is closed, and 1, which has passed through the knot circuit 12, is input to the gate terminal e of the micro-computer bus gate 8, so the micro-computer bus gate 8 is closed. open. Therefore, the common bus 6 is used by the microcomputer, and the peripheral circuit 4 is accessed by the microcomputer 1. At this time, when the microcomputer 1 obtains data, it outputs 1 from the interrupt output terminal a, and the synchronous flip-flop 10 (hereinafter referred to as synchronous FF), which has 1 inputted to the set terminal g, is set and outputs 1. Since 1 is input to both input terminals of the AND circuit 13, 1 is output, the synchronous FF 10 with 1 input to the reset terminal h is reset, and the interrupt FF 11 with 1 input to the set terminal i is set, and 1 is input to the interrupt input terminal b of the minicomputer 2 to generate an interrupt. When the minicomputer 2 accepts an interrupt, the minicomputer 2 requests data, and after performing the data request operations shown below, outputs 1 from the interrupt reset terminal c, and 1 is input to the reset terminal j. , interrupt FF11 is reset.

When the minicomputer 2 requests data, 1 is output from the data request signal terminal d, and 1 is input to the gate terminal f of the minicomputer bus gate 9, so the minicomputer bus gate opens and the gate terminal e of the microcomputer bus gate 8 is output. Since 0 is input through the note circuit 12, the microcomputer bus gate 8 is closed.
Therefore, the common bus 6 is used by the minicomputer, and the peripheral circuit 4 is accessed by the minicomputer 2. At this time, when the microcomputer 1 obtains data, it outputs 1 from the interrupt output terminal a, and the synchronous FF with 1 input to the set terminal g is set and 1 is output.
However, since 0 is input to one terminal of the AND circuit 13, 0 is output, and the interrupt FF 11 is not set while the data request signal is output.
After the minicomputer 2 reads the data, when the data request from the minicomputer 2 ends and 0 is output from the data request signal terminal d, the peripheral circuit 4 is disconnected from the minicomputer 2 and connected to the microcomputer 1, and the input of the AND circuit 13 is 1 is input to both terminals, so 1
is output, interrupt FF11 is set, and the minicomputer 2 is interrupted. The above method has been used to achieve synchronization so that the interrupt state does not change while the minicomputer 2 is requesting data. Also, in such a system, it is necessary to synchronize the clocks of the minicomputer and the microcomputer, so two circuits are required, one for interrupt synchronization and one for clock synchronization, which has the disadvantage of increasing the amount of hardware. .

(Problems to be solved by the invention) In order to eliminate these drawbacks, an object of the present invention is to synchronize interrupts without adding hardware by using a bus request signal and a bus permission signal, and also synchronize with a microcontroller. This will be described in detail below.

(Structure and operation of the invention) FIG. 2 shows an embodiment of the invention. 20 is a microcomputer device, 21 is a minicomputer, 22 is a microcomputer, 23
24 is a microcomputer bus, 25 is a minicomputer bus, 26 is a minicomputer bus gate that opens when 1 is input to the gate terminal q, and 27 is a peripheral circuit that is accessed from the microcomputer and minicomputer. This is an interrupt flip-flop that outputs 1 when set and outputs 0 when 1 is input to the reset terminal r.k is an interrupt output terminal that informs the minicomputer that the microcomputer has obtained data, and Input terminals, m is interrupt reset terminal, n is data request signal terminal, o is bus use request signal terminal (hereinafter referred to as HOLD terminal), p is bus use permission signal terminal (hereinafter referred to as HLDA terminal), q is minicombus gate 26 terminal. The gate terminal, r, is a reset terminal of the interrupt FF 27, s is a set terminal, t is a signal confirmation output terminal, and u is a signal confirmation input terminal.

When the minicomputer 21 does not request data, 0 is output from the data request signal terminal n. HOLD
The microcomputer 20 continues to operate while 0 is input to the terminal o, and 0 is output from the HLDA terminal.
The gate 26 with 0 input to the gate terminal q is closed, and the peripheral device 23 is being accessed by the microcomputer. At this time, when the microcomputer 20 obtains data, 1 is output from the interrupt output terminal k, and the interrupt FF 27 with 1 input to the set terminal s is set.
Input 1 to the interrupt input terminal l of the minicomputer 21 to generate an interrupt. When the minicomputer 21 accepts the interrupt,
The minicomputer 21 makes a data request, and after performing the following data request operations, outputs 1 from the interrupt reset terminal m, and outputs 1 from the reset terminal r.
The interrupt FF 27 to which is input is reset. A timing chart at this time is shown in FIG.

When the minicomputer 21 requests data, 1 is output from the data request signal terminal n, and 1 is input to the HOLD terminal o. After the current machine cycle is completed, the microcomputer 20 relinquishes the right to use the microcomputer bus 24 and makes the bus terminals high impedance. 1 is output to HLDA terminal p, and microcontroller 2
0 machine cycles are stopped. The mini-combus gate 26 with 1 input to the gate terminal q opens,
The peripheral circuit 23 is accessed by the minicomputer 21. After inputting the signal output from the signal confirmation signal output terminal t, the minicomputer takes in the data. At this time, since the machine cycle of the microcomputer 20 is stopped, no signal is output from the interrupt output terminal k. When the data request from the minicomputer 21 is completed, 0 is output from the data request signal terminal n.
When 0 is input to the HOLD terminal o, 0 is output from the HLDA terminal p, after which the microcomputer 20 gains the right to use the bus again and resumes operation. Gate terminal q
The minicomputer bus gate 26 to which 0 is input is closed, and the peripheral circuit 23 can no longer be accessed from the minicomputer 21. From then on, microcomputer 20 became minicomputer 2.
1 can be interrupted.

(Effects of the Invention) As explained above, in this embodiment, interrupt synchronization between the minicomputer and the microcomputer device is achieved using the bus use request signal and the bus use permission signal of the microcomputer, and the peripherals of the microcomputer device are synchronized with one gate. It has the advantage that the circuit can be accessed from the microcomputer and minicomputer, and at the same time synchronization can be achieved between the minicomputer and the microcomputer.

The present invention relates to a basic synchronization method between minicomputers and microcomputer devices, and simplifying this part facilitates the interface design between minicomputers and microcomputer devices that have many other handshake lines, and reduces costs. This reduces the amount of damage and improves reliability.

[Brief explanation of drawings]

FIG. 1 is a diagram showing a conventional interrupt synchronization method between a minicomputer and a microcomputer, FIG. 2 is an embodiment of the interrupt synchronization method between a minicomputer and a microcomputer according to the present invention, and FIG. 3 is a timing chart. 1...Microcomputer device, 2...Minicomputer, 3...
Microcomputer, 4...Peripheral circuit, 5...Microcomputer bus, 6...Common bus, 7...Minicomputer bus, 8...
...Microcomputer bus gate, 9...Minicombus gate, 10...Flip-flop for synchronization, 11...
Interrupt flip-flop, 12...not circuit,
13...AND circuit, 20...Microcomputer device, 2
1...Minicomputer, 22...Microcomputer, 23...Peripheral circuit, 24...Microcomputer bus, 25...Minicomputer bus, 26...Minicomputer bus gate, 27...
Interrupt flip-flop, a...interrupt output terminal,
b...Interrupt input terminal, c...Interrupt reset terminal,
d...data request signal terminal, e...gate terminal,
f...Gate terminal, g...Set terminal, h...Reset terminal, i...Set terminal, j...Reset terminal, k...Interrupt output terminal, l...Interrupt input terminal, m...Interrupt reset terminal, n...data request signal terminal, o...bus use request signal terminal, p...
Bus use permission signal terminal, q...gate terminal, r...
...Reset terminal, s...Set terminal, t...Signal confirmation signal output terminal, u...Signal confirmation signal input terminal, s24...Microcomputer bus signal, s25...
Mini-combus signals related to this device, so... bus use request signal, sq... mini-combus gate signal,
ss...Flip-flop set signal for interrupt, sl...
...Interrupt signal, sr...flip-flop preset signal for interrupt, su...signal confirmation signal.

Claims (1)

[Scope of Claims] 1. Consists of a minicomputer and a microcomputer device that exchange data via a bus while operating asynchronously, and the microcomputer device includes a microcomputer and peripheral circuits accessed by both the microcomputer and the minicomputer. , an interrupt flip-flop that instructs the minicomputer to interrupt when receiving an interrupt from the microcomputer; and an interrupt flip-flop provided on the bus between the output side of the microcomputer and the minicomputer;
and a minicomputer bus gate that opens in response to a bus use permission signal from the microcomputer, and in order to synchronize the data transfer request interrupt of the microcomputer device with the data transfer of the minicomputer, when the microcomputer obtains data, the interrupt flip-flop is activated. Input 1 to the set terminal of the minicomputer to set the flip-flop for the interrupt, input 1 to the interrupt input terminal of the minicomputer to generate an interrupt, and when the minicomputer receives an interrupt, the minicomputer sends a signal to the hold terminal of the microcomputer. inputting a data request signal to the microcomputer, causing the microcomputer to abandon use of the bus, and opening the minicomputer bus gate with the bus use permission signal, the microcomputer notifying the minicomputer that the bus can be used; The minicomputer accesses the peripheral circuit via the bus, and after the access is completed, the minicomputer outputs 1 to the reset terminal of the interrupt flip-flop, resets the interrupt flip-flop, and accesses the peripheral circuit. An interrupt synchronization method between minicomputers and microcomputers, characterized in that an access end signal indicating completion is input to a hold terminal of the microcomputer, and the microcomputer closes the minicomputer bus gate to use the bus.