JPH04131957A - Data transfer system - Google Patents

Abstract

PURPOSE:To decrease the number of signal lines of a common bus by providing a common signal line and plural input/output means which perform the mutual conversion of the address and data signals between a parallel form set for processing of each unit and a time-division form set for transfer of signals via the common signal line. CONSTITUTION:In regard of a common bus 30, the conventional address and data lines are used in common by an address/data line 4c (common signal line) and furthermore the signal lines (a, c, e and g) out of the arbitration lines are stored in a slave unit 3. Then the address and data signals are transferred in time division via the line 4c. In this respect, the input/output circuits 100 and 110 are provided to each of master units 1a - 1c and the unit 3 for mutual conversion carried out between the address and data signals of time division in parallel with each other. In such a constitution, the number of necessary common signal lines can be decreased and the wiring area can be reduced when the bus 30 is wired on a printed board.

Description

DETAILED DESCRIPTION OF THE INVENTION [Field of Industrial Application 1] The present invention relates to a data transfer system in which one or more master units and one or more slave units perform data communication via a common bus.

[Prior art] Fig. 7 shows a conventional programmable controller.
Multi-processor (also called multi-master)
1 shows the configuration of a data transfer system for transferring data between

In the figure, processors 1 (la, lb, lc) are classified and called master units based on the master-slave relationship in data transfer. In the figure, the number of master units is three, but in terms of system configuration, at least one is sufficient.

2 is a bus arbitration unit that manages the use of a common bus, and includes a plurality of master units la, lb.

When each common bus use request (REQ) is received from 1c, the bus use permission (A(J)) is issued only to the first master unit that receives the bus use request. If there is a master unit, the bus arbitration unit 2 may be built into that unit.

Reference numeral 3 denotes a slave unit which receives instructions from the master unit and becomes a data transfer partner, and is, for example, a shared memory. In the figure, there is only one slave unit, but there may be a plurality of slave units.

A common bus 4 includes a data line 4a for transferring data, an address line 4b for transferring an address to access the data, a control line 4c for transmitting control signals such as read/write signals for data transfer, and a code. It is composed of arbitration lines shown in (a) to h) and various bus lines such as power supply lines, but bus lines unnecessary for the explanation below are not shown in the figure.

The common bus 4 is structurally composed of a printed circuit board also called a back panel or a motherboard, and is electrically connected to the master unit Ii3 and the bus arbitration unit 2 through connectors.

[Problem to be solved by the invention]

In conventional multi-master type programmable controllers, when increasing the number of signal lines for the address bus and data bus in order to increase the amount of data handled and increase the speed of data transfer, the number of pins of the connection connector and the print The wiring area of the common bus on the board becomes abnormally large,
There has been a problem that programmable controllers have become larger and more expensive.

In view of these points, the present invention provides a data transfer system that can reduce the number of signal lines of a common bus without changing the circuit configurations of conventional master units and slave units. With the goal.

[Means to solve the problem]

In order to achieve such an object, the present invention connects a master unit and a slave unit by a bus, and connects an address signal generated by the master unit and an address signal generated in the master unit or the slave unit. In a data transfer system that transmits and receives data signals corresponding to between the master unit and the slave unit via the bus,
A common signal line provided in the bus for time-divisionally transferring the address signal and the data signal, and a common signal line provided between each of the master unit and the slave unit and the common signal line, It is characterized by comprising a plurality of input/output means for mutually converting the data signal into a parallel format for processing by each unit and a time division format for transferring via the common signal line.

[For production]

In the present invention, the address signal and data signal necessary for data communication between the master unit and the slave unit are transferred in a time division manner via a common signal line and separated into parallel signals, so that the address and data signals are There is no need to have a separate one for each.

In addition, when multiple master units are arranged and bus arbitration processing is performed, the data transfer speed will not be lower than the transfer speed of conventional systems by transferring the address at the same timing as acquiring the right to use the bus. .

〔Example〕

FIG. 1 shows the system configuration of a multi-master system to which the present invention is applied. In this figure, components having the same functions as those in FIG. 7 (conventional example) are given the same numbers, and detailed explanation thereof will be omitted.

In this embodiment, the address line 4b and data line 4a of the conventional common bus 4 (see FIG. 7) are shared by an address/data line 4c (common signal 11 of the present invention), and the arbitration line of the common bus 4 is Of which (a), (c), (e)
.

Each signal line in (g) is input to the slave unit 3. In this embodiment, address signals and data signals are transferred in a time-division manner by the address/data line 4c in FIG. For this purpose, each master unit 1a to lc and slave unit 3 are provided with an input/output circuit (input/output means of the present invention) 100° 110 for mutually converting time-division address signals and data signals in parallel. There is.

Next, various bus lines that make up the common bus 30 will be explained. Note that an asterisk in front of the signal name indicates negative logic, and no mark indicates positive logic.

(a) is a clock pulse (hereinafter abbreviated as *CLOCK), and the common bus operates in synchronization with this. That is, this embodiment shows a synchronous bus.

(b), (d), and (f) are common bus use request signals (hereinafter abbreviated as *REQn, where n collectively refers to the identification signal of the master unit) from each master unit.

(c), (e), and (g) are common bus use permission signals (hereinafter referred to as *ACK) output by the bus arbitration unit.
(abbreviated as n).

*REQn and *ACKn are prepared for the number of master units, and are connected to the bus arbitration unit in a 1:1 correspondence.

(h) is a busy signal (hereinafter abbreviated as *BUSY) indicating that data is being transferred using the common bus.

Control line (CONTROL), address line (A
The address/data line 4d (ADDRESS/DATA) has already been described, so its explanation will be omitted, but in FIG.
), the address line and data line are shared.

In addition, in the following explanation, only a signal indicating the direction of data transfer (hereinafter abbreviated as *DIR) appears as a control line, but in actual data transfer, several more signals exist, and these signals are not included in the present invention. Since they are not directly related, they are not shown in all the explanatory drawings.

FIG. 2 shows an example of the common bus input/output (interface) circuit 100 on the master unit 1 side in FIG.

In FIG. 2, 10a and lOb are flip-flops, lla to llj are gates, and these circuits determine the operating conditions of the input/output circuit 100 regarding signal exchange with the common bus. 12a to 12c are bus drivers. In the figure, gates 11e and llf and bus drivers 12a to 12c are equipped with three-state or oven collector (oven drain) type ICs (integrated circuits) to select data signals according to the transfer direction.
is used, and the potential when the common bus 30 is vacant is determined by a terminating resistor (not shown).

What should be noted in the same figure is the bus driver Lea and 12
The point is that the output of b is connected just before the common bus.

That is, the address signal (ADH
) and the data signal (DT) are alternately connected to the address/data line (ADDRESS/DATA) 4d of the common bus 30, thereby making it possible to transfer the address signal and the data signal in a time-division manner. Flip-flop 10b outputs an instruction signal for this switching. Specifically, the reset state of the flip-flop 10b (the Q terminal of the flip-flop 10b is set to bit "
When *ACKn is received at 0″), gate lid, ll
j to activate the bus driver 12a and output the address signal on the master unit side to the common bus 30.

Conversely, the set state of the flip-flop 10b (the same bit “
1"), one of the bus drivers 12b and 12c is activated through the gates llh and llj, and the common bus 3
Data input/output is performed for 0.

Since the transfer direction of the data signal is reversed according to the read/write instructions from the master unit 1 side, the bus driver 12b
(for output) and 12c (for input) are connected in antiparallel, and bus drivers 12b and 12c are selected by a direction indicating signal (DIR) using a read/write signal from the master unit 1 side.

A reset pulse (*RESET) is generated when the power is on, and initializes the flip-flops lOa and 10b. A start signal (START) and a stop signal (END) are signals for instructing the start and stop of bus access, respectively.

FIG. 3 shows the circuit configuration of the bus arbitration unit 2 in FIG. 1.

In FIG. 3, 20 is a clock generation circuit which supplies *CLO(J) to the common bus through a gate 21a. The frequency of the clock generated by the clock generation circuit 20 varies depending on the system, but in this example, it is approximately 10MHz.

21b to 21i are gates. As is clear from the figure, this embodiment shows a three-level parallel fixed priority arbitration circuit.

FIG. 4 shows the circuit configuration of the slave unit 3 in FIG. 1.

In FIG. 3, 30 is an address latch, and a gate 31
During the bus usage right acquisition cycle by a to 31c (*
The address signal on ADDRESS/DATJI with ACKn="1" is held in synchronization with the *CLOCK signal.

31d to 31f are gates, and 32a and 32b are bus drivers. During data transfer cycle (* BUS
bus driver 3 by the *DIR signal of Y=“1”).
Either 2a or 32b is activated. 33 is a memory. Corresponding to the master unit 1, the address latch 30 and bus drivers 32a and 32b are connected on the common bus side so that the slave unit 3 side can also input and output information on the ADDRESS/DATA line in a time-sharing manner.

The configuration of each part has been explained above, and the operation of the circuit will be explained below based on the timing chart of FIG.
As already mentioned, data communication between the master unit 1 and the slave unit 3 via the common bus 4 is performed during the bus usage right acquisition cycle (from time t1 to t2 in the figure) and the data transfer cycle (from time t2 to t4). It can be broadly classified into.

Master unit 1 that wants to access the bus is
A starting signal 5TART of one clock width is generated from time t2. With this signal, input/output circuit 1 of master unit 1
00 flip-flop 1Oa (see Figure 2) is at time t
It is set to 1, and *REQ2 (in the case of FIG. 5, only the master unit 1b has issued a request) is output on the common bus 4. Bus arbitration unit 2 immediately returns the ACK2 signal since there are no other requests (the bus is also free). In response to this, master unit lb sends an ACK2 signal to the ADDRESS/DATA line while the CK2 signal is being generated. An address signal is output.When this address signal is 1 or more held in the address latch 30 of the slave unit 3 at time t2, the cycle for acquiring the right to use the bus is completed.

Master unit lb, which has obtained the right to use the bus, subsequently moves to a data transfer cycle. First, at the clock input timing at time t2, the flip-flop lOb is set by the ACK2 signal*BUSY becomes "1", and at the same timing, DIR, this DIR, becomes bit "1".
This instructs the slave unit 3 that the direction of data transfer is the output from the master unit 1.

The operation timing in FIG. 5 shows that the output from the master unit 1 is executed in two clocks.
The bus driver 12a is selected by the IR signal, and at time t
The DATA signal output in 2 is ADDRESS/DAT
Transferred to line A.

On the other hand, in the slave unit 3, when the ACK2 signal is generated, it is latched by the ADDRESS signal and the latch 30 in FIG. 4, and the address is input to the common memory 33. Also, *D
The bus driver 32a in FIG. 4 is selected by the generation of the IR signal, and the DATA generated simultaneously with the generation of the DIR signal is selected.
The signal is data input to the common memory 33.

In addition to this embodiment, the following examples can be cited.

l) In this embodiment, input/output circuits 100 and 110 for synthesizing address signals and data signals into time-division signals are provided in the master unit 1 and slave unit, respectively. It may be externally connected to the unit or slave unit.

In this case, as shown in FIG. 6, the input/output circuits too, t are connected to the unit connection connectors provided on the printed circuit board.
Once io is installed, the conventional master unit and slave unit can be used as is.

2) In this embodiment, a multi-master system in which a plurality of master units are installed is taken as an example, but if there is only one master unit, the arbitration unit 2 is not required. In this case, the input/output circuit 100 on the master unit 1 side
It is preferable to configure the input/output circuit so that the first clock of the CLOCK signal transfers the address signal to the address/data line, and the second clock transfers the data signal to the address/data line.

[Effects of the Invention] As described above, according to the present invention, address signals and data signals are time-divisionally transmitted and converted into parallel signals for processing by the master unit and slave units.
Signal lines for transmitting address signals and data signals can be shared. For example, when transmitting a 32-bit data signal, 32 data lines and 32 address lines are required in conventional systems, but according to the present invention, 32 common signal lines are required. As a result, when wiring the common bus on a printed circuit board, the wiring area can be reduced.
This can contribute to miniaturization of the entire device.

[Brief explanation of the drawing]

1 is a block diagram showing the system configuration of an embodiment of the present invention, FIG. 2 is a circuit diagram showing the configuration of the input/output circuit 100 in the master unit 1 of FIG. 1, and FIG. 3 is the bus arbitration unit of FIG. 1. 2. FIG. 4 is a circuit diagram showing the configuration of the slave unit 3 in FIG. 1. FIG. 5 is a timing chart showing the signal generation timing of the embodiment of the present invention. FIG. 7 is a block diagram showing the system configuration of a conventional example. 1, la, lb, lc...master unit, 2
... bus arbitration unit, 3 ... slave unit, 100.110 ... input/output circuit. 1st bus 1 round stop Unit 2 Taruhachi 1 circuit diagram 3 Figure 1 Slave uniform in the 1st school To 3 lectures 1 bus 7 times Each figure 4 Figure 1 circuit diagram Figure 5

Claims (1)

[Claims] 1) A master unit and a slave unit are connected by a bus, and an address signal generated by the master unit and a data signal generated in the master unit or the slave unit and corresponding to the address signal are transmitted. In a data transfer system that transmits and receives data between the master unit and the slave unit via the bus, the common signal line is provided in the bus and is used to transfer the address signal and the data signal in a time-division manner; A time division mode is provided between each of the master unit and the slave unit and the common signal line to transfer the address signal and the data signal in a parallel manner for processing in each unit and by the common signal line. 1. A data transfer system comprising a plurality of input/output means for mutual conversion.