JPH0554749B2 - - Google Patents

Description

[Detailed Description of the Invention] [Field of Industrial Application] The present invention is directed to a plurality of microcomputers (hereinafter referred to as CPUs) that control various functions inside an electronic device having a synchronous signal processing system, such as a video device.
The present invention relates to a communication method used when communicating between LSIs or between a plurality of video information devices such as a VTR, a camera, a tuner, and a timer unit in a system.

[Conventional technology]

Recent VTRs are becoming more multifunctional, smaller, and cheaper. In line with this trend, control systems, or system controllers (hereinafter referred to as system controllers), have become increasingly complex, and due to constraints such as memory capacity, processing time, and number of input/output pins, system controllers require multiple CPUs.
is increasingly being used. Besides, the CPU
Due to lower prices, there is a trend to replace feature hardware with software processing, and there is an increasing demand for peripheral operations and controls such as remote control, which previously required going through a system controller. The fact that unused lines have come under the control of Cisco is also a sign that multiple
This is spurring the trend of using CPUs.

The 10th method for configuring the system in this case is
As shown in the figure, these multiple CPUs are centrally
on each substrate 1, and each
It is conceivable to connect the functional boards 2 to 5 that perform the functions controlled by the CPU to centrally perform control.

However, as is clear from the figure, this configuration has the disadvantage that the number of wire connections is extremely large, which increases the number of manufacturing steps and reduces reliability.

One possible way to avoid this drawback is to modularize each function as a functional device consisting of a CPU or LSI that controls that function, and a circuit block that performs that function, and perform distributed processing.

As described above, when performing distributed processing using a plurality of functional devices, problems arise in how to transmit control data for each functional device and how to transmit data from this functional device.

One of the methods is as shown in Figure 11.
A non-bus line system can be considered in which functional devices that require data transmission are connected to form a mesh structure. In other words, it is a method that decentralizes not only processing but also information. However, this method has the disadvantage that the mesh structure makes the processing very complicated, making debugging and modification difficult.

Therefore, a method was devised in which the data communication lines between each functional device were made into a bus line to decentralize processing but centralize information data. In this case, if data is communicated as parallel data, there will be a large number of communication lines, so the bus line is a serial bus line for transmitting serial data.

FIG. 12 is a diagram showing the connection state of an intra-system communication method that adopts such a centralized information distributed processing method.
One of the plurality of functional devices is the master functional device, the other functional devices are the slaves, and the CPU 10 of the master functional device and the CPUs 11 to 15 of the plurality of slave functional devices
A serial bus line 16 connects between the two. Then, CPU11 to 1 of each slave functional device
5 and functional blocks 11F to 15F are connected in the same way as usual.

According to such information centralized distributed processing method,
It has the following advantages:

That is, since the number of wire connections is significantly reduced, manufacturing man-hours can be reduced and reliability can be improved. In addition, communication with the outside is easy due to the centralization of information. In other words, communication with the outside only needs to be performed with the CPU of the functional device dedicated to communication with the outside, so it is possible to communicate with the editing machine, remote control, and home bus. Easier to interface. Additionally, all information flows through a common communication channel, making expansion easier.
Furthermore, functional modularization makes it possible to standardize functional devices across fibers, making it possible to handle multi-product, variable-volume production. In this case, each functional device is tested at the module level and its operation is guaranteed before use, improving product reliability. By modularizing this function, large-scale systems can be easily completed, and costs can be reduced by mass production at the module level.
Together with the reduction in assembly man-hours, it is possible to significantly reduce the cost of the system.

The following is known as a specific example of a communication method within an information centralized distributed processing system having the above-mentioned characteristics.

In other words, since many recent one-chip CPUs have a built-in serial port, this communication is performed using this serial port. Here, silal port refers to the following.

That is, Fig. 13 shows an example of an 8-bit serial port. In the figure, 21 is an 8-bit shift register, and its serial input terminal is connected to the CPU 20.
Connected to serial input terminal SI. Further, the serial output terminal of this shift register 21 is connected via a latch circuit 22 for one bit and an output gate 23.
Connected to the serial output terminal SO of the CPU 20.

Further, SCK is the clock terminal of the CPU 20, and when the clock changeover switch 24 is switched to the terminal A side, the clock INCK from the internal clock generation source 25 in this CPU 20 is sent to the clock terminal of the shift register 21 via this switch 24. When the switch 24 is switched to the terminal B side, the clock EXCK input from the outside through the clock terminal SCK is supplied to the clock terminal of the shift register 21.

In addition, the parallel input/output terminal of the system register 21
It is connected to the internal data bus of the CPU 20.

The INCK and EXCK clocks provide 8 bits, or 8 pulses, only during communication, and by supplying these 8 clock pulses to the system register 21, the 8-bit data stored at that time is is transferred to the serial output terminal SO via the latch circuit 22 and output gate 23, and the 8-bit data input to the serial input terminal SI is transferred to the system register 21.
be taken in.

Figure 14A shows the clock pulse supplied to this system register 21, Figure 14B shows the 8-bit data being written, and Figure 14C shows the 8-bit data being read. Data is read and data is written on the rising trailing edge of the clock pulse.

The latch circuit 22 is used to hold one bit of read data during writing and reading in this manner.

Then, when the counter 26 counts 8 of these shift cross pulses INCK or EXCK, an interrupt signal is obtained from this, and the data taken into the shift register 21 is read out and transferred to the internal data bus. Ru. Further, the next sending data is written into the shift register 21.

Communication within the information centralized distributed processing system described above is performed using a functional device equipped with a CPU having a serial port as described above. That is,
Figure 15 is an example of this, in which the serial output terminal SO of the serial port of the CPU 30 of the master functional device is connected to the CPU 31 of the slave functional device,
Connect to serial input terminal SI of 32 serial ports, and connect to serial input terminal SI of CPU 30.
are connected to the serial output terminals SO of the CPUs 31 and 32, respectively. In addition, the clock terminal of CPU30
Connect SCK to clock terminals SCK of CPUs 31 and 32. And in this case, the master's
The clock selection switch 24 of the CPU 30 is at terminal A.
When switched to the slave CPU31,
The clock changeover switch 24 of 32 is switched to the terminal B side. Therefore, the clock terminal SCK is
In the master CPU 30, it becomes an output terminal, and in the slave CPUs 31 and 32, it becomes an input terminal.

In addition, in this example, the master CPU30
is provided with as many pairs of request input terminals and output terminals as there are slave functional devices. In this example, since there are two slave functional devices, a request input terminal RQI ₁ , an output terminal RQO ₁ , a request input terminal RQI ₂ , and an output terminal RQO ₂ are provided.

On the other hand, the slave CPUs 31 and 32 are each provided with a pair of request input terminals RQI and output terminals RQO.

Then, the request input terminals RQI 1 and RQI 2 of the master CPU 30 are connected to the slave's request input terminals RQI ₁ and RQI ₂ , respectively.
The request output terminals RQO 1 and RQO 2 of the master CPU 30 are connected to the request output terminals RQO of the CPU 31 and 32 respectively, and the request output terminals RQO ₁ and RQO ₂ of the master CPU 30 are connected to the slave CPU 31.
and 32 request input terminals RQI, respectively.

Then, when the need for communication arises, for example when the mode changes on a VTR, a request is issued and communication is performed. For example, when the CPU 31 needs to communicate with the slave, the request output terminal
The request signal supplied from RQO to the request input terminal RQI ₁ of the master CPU 30 becomes, for example, "1", and communication from the CPU 31 to the CPU 30 is activated.

In the master CPU30, in response to this, this
After the other work done by CPU 30 and other communications are completed, the master CPU 30
Request output terminal RQO ₂ of slave CPU
The request signal supplied to the request input terminal RQI of CPU 31 is set to "1", and the request signal supplied to the request input terminal RQI of CPU 31 is set to "1".
Activate sending to. This enables communication between the slave CPU 31 and the master CPU 30. Then, eight internal clocks INCK are obtained from the CPU 30, which are supplied to its built-in shift register 21, and are also supplied to the built-in shift register 21 of the slave CPU 31 through the clock input/output terminal SCK, and are stored in each shift register 21. The data that had been stored is read out by the leading edge of this clock pulse INCK, and is transferred from the output terminal SO to the input terminal of the other side.
is supplied to the input terminal of its built-in shift register 21 through SI, and at the trailing edge of the shift clock INCK,
Each is written into the shift register 21. In this way, the data of the CPU 31 and the data of the CPU 30 are simultaneously communicated, and the data in the shift registers 21 of the CPUs 30 and 31 are exchanged, so to speak.

When this communication is completed, 8-bit parallel data is read out from the shift register 21 in each CPU 30 and 31 by an interrupt signal and supplied to the internal bus, and processing is performed according to the data.

During this communication, if there is another work request, such as a remote control interrupt request or a timer interrupt request, which should take priority over the communication, the request is stopped, that is, the request signal is set to "0" and the communication is not started. is interrupted and the routine for that interrupt is executed. At this time, the other party's CPU becomes aware of this based on the state of the request signal, considers the communication to be a failure, and tries again after a while.

Note that the clock signal of the shift register 21 is
It is not necessary to always output from the master CPU 30, and it may be output from the slave CPU side.

[Problem that the invention seeks to solve]

In the case of the conventional communication method described above, communication is performed by issuing a request only when the need for communication arises, such as when the mode changes, so it is necessary to constantly monitor whether there is a request. In addition, as mentioned above, communication management must be considered, such as considering priorities with other tasks and when communication requests from other slave functional devices overlap. It's difficult and bug-prone. Furthermore, since debugging is time consuming, the manufacturing period becomes longer, the number of man-hours increases, and efficient design cannot be achieved.

Furthermore, since communication is completed only once, there is also the disadvantage that if incorrect data is sent, the device will remain in the incorrect state until the next request is made.

[Means for solving problems]

Figure 1 shows an example of the basic configuration of this invention, in which there are five functional devices, the CPU 40 of one of them is the master, and the CPU 40 of the other functional devices is the master.
This is a case where the CPUs 41 to 44 are slaves.

In this example as well, the serial output terminal SO of the master CPU 40 is connected to the serial input terminal SI of the slave CPUs 41 to 44, and the serial input terminal SI of the master CPU 40 is connected to the serial output terminal SO of the slave CPUs 41 to 44, respectively. Connected and master CPU40
Serial clock pin SCK and slave
Serial clock terminals SCK of CPUs 41 to 44 are connected to each other.

And in this case the master's functional device's
Chip select signal CS ₁ ~ from CPU 40
CS ₄ is CPU 41 to 4 of each slave's functional device.
4 chip select terminal. In this case, the chip select signals CS ₁ -CS ₄ are signals whose phases are shifted so that the periods in which they are "0" do not overlap with each other in time, as shown in FIGS. 2A to 2D. In addition, E in the same figure shows the vertical synchronization pulse VD from the synchronization signal processing system of this system, for example, the horizontal and vertical synchronization system of video information equipment, and the chip select signal.
CS ₁ to CS ₄ are obtained in vertical cycles in synchronization with this vertical synchronization pulse VD.

[Effect]

When the chip select signal CS ₁ becomes "0", communication becomes possible between the master CPU 40 and slave CPU 41, and the period when this signal CS ₁ is "0"
At T ₁ , master CPU40 or slave
The data stored in the shift register of each CPU 40 and 41 is transferred to the shift register of the other party by clock pulses of the required number of bits from the CPU 41. In other words, simultaneous bidirectional communication is performed.

Next, when the chip select signal CS ₂ becomes "0" during the period T ₂ , communication becomes possible between the master CPU 40 and the slave CPU 42.
Also, the period during which the chip select signal CS ₃ is “0”
At T ₃ , the master CPU40 and the slave
Communication becomes possible with the CPU 43, and when the chip select signal CS ₄ becomes "0" at period T ₄ , the master CPU 40 and slave
Communication becomes possible with the CPU 44, and simultaneous bidirectional communication is performed in the same manner as in the period _T1 .

One set of the above periods T ₁ to T ₄ is repeated in a vertical period.

〔Example〕

FIG. 3 shows an embodiment of the present invention, and this example is an example in which the present invention is applied to internal communication of a VTR.

Further, in this example, the master functional device is a mode controller, which has a CPU 50. In addition, the slave functional devices are tuner, timer, and mechanical controller, each with CPU5
1, 52, 53. And these
Each of the CPUs 50 to 53 has an 8-bit serial port as shown in FIG. 13 described above.

A vertical synchronizing pulse VD (Fig. 4A) is supplied to the CPU 50 of the mode controller through an input port, so that communication is performed in vertical cycles in phase synchronization with this vertical synchronizing pulse VD as described later. has been done.

Serial output terminal SO of CPU50 and CPU51~
53's serial input terminal SI is connected, and the CPU 50's serial input terminal SI and CPU51~
53 serial output terminal SO is connected. In addition, the serial clock terminal of CPU50-53
SCKs are connected together. In this example, as in the previous example, switch 24 of the master CPU 50 is
is switched to the terminal A side, and the switches 24 of the slave CPUs 51 to 53 are switched to the terminal B side, so that the clock is generated only from the master CPU 50.

Furthermore, chip select signals CS ₁ to CS ₃ are supplied from the CPU 50 of the mode controller, which is a master functional device, to the respective chip select terminals of CPUs 51 to 53 of the tuner, timer, and mechanical controller, which are each slave functional device. The CPUs 51 to 53 and the CPU 50 can sequentially communicate with each other in periods that do not overlap in time within one vertical period. In other words, the master CPU 50 manages the communication, and the communication is periodically repeated in phase synchronization with the vertical synchronization signal of the video signal.

The communication status will be explained in more detail below.

That is, the chip select signal CS ₁ (Figure 4B)
During the period TA during which the CPU 51 of the tuner and the mode controller become low level, communication becomes possible between the CPU 51 of the tuner and the CPU 50 of the mode controller, and the output gates 23 of both CPUs 50 and 51 are enabled as shown in FIG. Data DM (J in FIG. 4) and data DS ₁ (K in FIG. 4) are written into the respective shift registers 21. When data DM and DS ₁ are prepared in this way, CPU5
0 to 8 clocks CLK (Fig. 4 I) are supplied to the built-in shift register 21, and
A clock CLK is also supplied to the built-in shift register 21 of the CPU 51 through a terminal SCK. Therefore, the transmission data DM of CPU50 is
1 shift register 21, and the CPU 5
The transmission data DS ₁ of 1 is taken into the shift register 21 of the CPU 50 . In this way, when bidirectional simultaneous communication of 1 word (8 bits) of data is completed,
As shown in FIGS. 4E and 4F, each received data is read out in the form of parallel data and supplied to the internal bus.

In this example, two words of data are communicated in one cycle between the mode controller and the tuner. For this reason, CRU50
and 51, the next second word of data is then written to the shift register 21, and then eight clocks CLK (I in the same figure) are sent from the CPU 50.
is obtained again, and the second word data DM and DS ₁
Two-way simultaneous communication is performed.

When this second word communication is completed, both CPUs
Serial ports 50 and 51 are disabled.

Examples of communication data between the mode controller and the tuner include output data of the tuner CPU 51 such as display data of the current channel on the display unit 511, channel position, band information, and tuning preset data.
Channel selection commands and other input data are input to the CPU.
Write request data from the CPU to the non-volatile memory 512 connected to the tuner CPU 51, for example β
, the last data of the velocity mode of β, etc.

Next, when the chip select signal CS ₂ (Fig. 4C) reaches low level TB, the timer starts.
Communication is now possible between the CPU 52 and the CPU 50 of the mode controller, and the data DM of the CPU 50 and the CPU
Simultaneous bidirectional communication with 52 data DS ₂ is performed. In this example, the distance between both CPUs 50 and 52 is 1
Communication is one word per cycle.

In this example, the timer CPU 52 receives the remote control signal from the remote control receiver 521 and drives the fluorescent display tube 522.
Output data from the CPU 52 includes remote control reception data, timer recording and power control data, and input data include counter values, VTR function modes, and the like.

Next, when the chip select signal CS ₃ (D in Fig. 4) becomes low level TC, the CPU 53 of the mechanical controller and the CPU of the mode controller
Communication between 50 and 50 is now possible, and the
And as shown in M, the data DM of CPU50
Simultaneous bidirectional communication is performed with the data DS ₃ of the CPU 53. In this example, communication between the CPUs 50 and 53 is one word per cycle.

The mechanical controller receives information from the mode controller about the mode to which the mechanical deck 531 should transition next, and sends out the current mode of the mechanical deck 531, count information on the counter display section 532, etc. The output data of the CPU 53 is the counter value,
Information such as the current mode and the next mode, or the next mode and the transition code, status such as β/β, etc., is input data such as a mode command indicating what mode to be in next, instructions such as β/β, etc. Data such as status commands and commands such as counter reset are listed respectively.

As mentioned above, chip select signals CS ₁ to CS ₃
The period TA ~ TC specified by the signal CS ₁ ~
Since CS ₃ is a signal synchronized with the vertical synchronization pulse, communication is periodically performed between the CPU 50 and the CPUs 51 to 53 repeatedly in phase synchronization with the vertical synchronization pulse.

And each slave's CPU51~5
In No. 3, other work can be done outside the communication interval TA to TC, so even if the above-mentioned periodic communication is performed, the other work will not be hindered. On the other hand, since the communication period is fixed, when doing other tasks in a time-sharing manner, it is possible to prevent one task from being interrupted due to communication.
You can also easily manage your time.

Note that in the master CPU 50, instead of allocating one vertical cycle entirely to internal communication, a pause period is provided, and this pause period is used for this purpose.
To perform external communication between the VTR and video cameras and other peripherals and other tasks.

Note that in this case, the master CPU 50 may of course be used exclusively for communication.

The above is a case where each functional device is provided with a CPU having a serial port equipped with a shift register as shown in Figure 13.
It is also possible to use an LSI that is equipped with a serial part as shown in FIG.

It is also possible to use a CPU that does not have a serial port with a shift register.

That is, when this CPU 60 is installed in a slave functional device, the serial output terminal SO of the master CPU, which has a serial port equipped with a shift register, is connected to the input port 61, as shown in FIG. clock terminal
SCK is connected to output ports 62 and 63, respectively, and chip select signal CS is supplied to interrupt input terminal INT. The select signal CS may be input through an input port. Then, a signal is output from another output port 64 to enable the lines from the output ports 62 and 63, a clock is created by software in this CPU 60, and data is read and written bit by bit by software. master's
A clock created by this software is supplied to the CPU, and this is used as the shift clock for its built-in shift register. In other words, connect the master CPU's clock selector switch to terminal B.

Also, it does not have a shift register like this
When using the CPU as a master functional device, as shown in Figure 6, output port 71 is the serial output terminal SO, input port 72 is the serial input terminal SI, output port 73 is the clock output terminal SCK, and the output port 74 is used as the output terminal for the chip select signal, and in this case as well, a clock is created using software and transmitted to the slave CPU side, while the master CPU reads and writes data bit by bit using software.

In addition, especially when processing a lot of data, the function of the slave device as shown in Figure 7 is
Regarding the CPU 80, the CPU 9 of the slave functional device is further connected via the serial bus line 81.
0 is provided for these slave devices.
When it is necessary to communicate between the CPUs 80 and 90, as shown in FIG.
As shown in FIG. 8, two serial ports may be provided, and communication between the slave CPUs 80 and 90 may be carried out during periods when communication between the master CPU 70 and slave CPU 80 is inactive by time division multiplexing, as shown in FIG.

Furthermore, if the slave CPU 80 has only one serial port, as shown in Figure 9,
A switch 100 is installed on the serial bus, and the slave CPU 80 and master CPU are
What is necessary is to cut off the communication path with 70 and connect the communication path with slave CPUs 80 and 90.

Furthermore, there are also CPUs that do not have an 8-bit shift register as described above but are equipped with a serial port that has a 4-bit shift register, but such a CPU can be compared with a CPU that has an 8-bit serial port. When used for communication, communication can be performed without any problems by issuing a 4-bit clock twice from the CPU side having this 4-bit serial port, taking into account the time required to take data into the internal bus.

Further, the clock may not be created by the master CPU or slave CPU, but a clock created by another CPU or hardware may be used in common. At this time, a clock generation timing signal is given to this clock generation means from the master CPU.

The above explanation has been given using the example of communication between functional devices inside a VTR, but it is not limited to internal communication of a single electronic device like this; for example, it can also be applied to a video equipment system consisting of a VTR, video camera, monitor receiver, etc. When considered, it goes without saying that the present invention can also be applied to communication between a VTR and a video camera, a VTR and a monitor receiver, etc. within this system.

〔Effect of the invention〕

According to this invention, the general effects of communication within the information centralized distributed processing system described above, namely, reduction in manufacturing man-hours due to fewer wire connections and fewer pins, ease of manufacturing, high serviceability, and multiplication due to functional modeling, can be achieved. In addition to the effects of making variable production possible, the following effects are achieved by periodically performing communication in synchronization with the synchronization signal of the synchronization system.

In other words, by synchronizing communication, even if a communication error occurs, correct data is immediately sent and the normal state is restored, reducing the error rate and improving reliability. Further, since the communication is periodic and communication is managed only on the master side, communication management is very easy, and communication bugs can be easily debugged.

Further, since the communication is synchronous communication that is phase-synchronized with the synchronization signal of the synchronization system of the system, processing can be easily performed based on information that performs processing in synchronization with this synchronization signal. For example, when editing on a VTR, the command data is phase-locked to the vertical sync pulse, so you can accurately determine how far from now to connect the signal. In addition, it becomes easy to communicate frame numbers and feed numbers using time codes as communication data.

[Brief explanation of the drawing]

Fig. 1 is a block diagram of an example of the basic configuration of this invention, Fig. 2 is a diagram for explaining the same, Fig. 3 is a block diagram of an embodiment of this invention, and Fig. 4 is a diagram for explaining the same. Figures 5 and 6 are diagrams showing other examples of serial ports, and Figures 7 to 9 are communication methods between both devices when there is a slave functional device in addition to the slave functional device. Figures 10 to 12 are diagrams for explaining an example, and Figures 10 to 12 are diagrams showing examples of processing methods for various functions of the system.
Figure 3 is a block diagram showing an example of a serial port.
FIG. 14 is a diagram for explaining the same, and FIG. 15 is a diagram showing an example of a communication method using this serial port. 40 is the CPU of the master functional device, 41
~44 is the CPU of the slave functional device, SO is the serial output terminal, SI is the serial input terminal,
SCK is a serial clock terminal.

Claims (1)

[Claims] 1. In a system that includes multiple functional devices having serial input terminals, serial output terminals, and clock terminals, and a synchronous signal processing system, one of the multiple functional devices is designated as a master, the others are designated as slaves, and the serial number of the master functional device is Input terminal and serial output terminal of each slave functional device, serial output terminal of the above master functional device and serial input terminal of each slave functional device, clock terminal of the above master functional device and clock terminal of each slave functional device are connected to each other, and a chip select signal is supplied from the master's functional device to each slave's functional device, and this chip select signal exclusively allows communication between the master's functional device and each slave's functional device. An intra-system communication method that is performed sequentially and periodically in synchronization with the synchronization signal.