JPS61166244A - Communication system within system - Google Patents

Abstract

PURPOSE:To attain ease of communication management and ease of debugging of communication bug by executing communication periodically synchronously with a synchronizing signal of a synchronous system. CONSTITUTION:Chip select signals CS1-CS3 are fed to each chip select terminal of CPU51-53 for a tuner, a timer and a mechanism controller being each slave function device from a CPU50 of a mode controller so that the CPU51-53 and the CPU50 are communicated at a period not overlapped timewise within one vertical period. That is, the master CPU50 manages communication and the communication is repeated periodically in phase locking with the vertical synchronizing signal of a video signal.

Description

[Detailed Description of the Invention] [Field of Industrial Application] This invention is directed to a plurality of microcomputers (hereinafter referred to as CPUs) and LSIs that control various functions inside an electronic device having a synchronous signal processing system, such as a video device. The present invention relates to a communication method used when communicating between a plurality of video information devices, such as a VTR, a camera, a tuner, and a timer unit in a system including these devices. .

[Conventional technology]

Recent VTRs are becoming more multi-functional, smaller, and cheaper. In this trend, control systems, or system controllers (hereinafter referred to as system controllers), have become increasingly complex.
Due to constraints such as memory capacity, processing time, and number of input/output pins, system computers often use multiple CPUs.

Furthermore, with the drop in CPU prices, there is a trend to replace feature hardware with software processing, and the need for peripheral operations and control, such as remote control, has increased. The trend of using multiple CPUs is also spurred by the fact that lines that did not need to be routed through the computer are now being managed by the system controller.

In this case, as shown in Figure 10, the system configuration method is to centrally connect these multiple CPUs to one board (1).
It is conceivable to centrally perform control by connecting functional boards (2) to (5) that perform the functions controlled by each CPU to this board (1).

However, as is clear from the figure, this configuration has the disadvantage that the number of wire connections is extremely large, which increases the number of manufacturing steps and reduces reliability.

As a way to avoid this drawback, it is conceivable to perform distributed processing by dividing each function into a functional device consisting of a CPU or LSI that controls the function, a circuit block, etc. that performs the function, and performs distributed processing.

As described above, when performing distributed processing using a plurality of functional devices, problems arise in how to transmit control data to each functional device and how to transmit data from this functional device.

As one method, a non-pass line system can be considered, as shown in FIG. 11, in which functional devices that require data transmission are connected to form a mesh structure. In other words, it is a method that decentralizes not only processing but also information. However, this method has the disadvantage that the fine-grained structure makes the processing very complicated, making debugging and modification difficult.

Therefore, a method was devised in which the data communication lines between each functional device were made into a path line to decentralize processing but centralize information data. In this case, if the data is communicated as parallel data, there will be a large number of communication lines, so
The pass line is a serial pass line that transmits serial data.

Figure 12 is a neo-diagram showing the interconnection state of the intra-system communication method that adopts the information distribution processing method under construction.One of the multiple functional devices is the master functional device, and the other functional devices are the slaves. As a serial path line (1), a serial path line (1
6) Connect.

Then, the CPU (11) of each slave functional device ~
(15) and functional blocks (IIF) to (15F)
Connect as usual.

Such an information centralized distributed processing method has the following advantages.

That is, since the number of wire connections is significantly reduced, manufacturing man-hours can be reduced and reliability can be improved. In addition, communication with the outside is easy due to the centralization of information.In other words, communication with the outside can be performed with the CPU of a functional device dedicated to communication with the outside, so it is possible to communicate with the outside, for example, with the CPU of a functional device dedicated to communication with the outside. It becomes easier to interface with. Additionally, all information flows through a common communication channel, making expansion easier.

Furthermore, functional modularization makes it possible to standardize functional devices across models, making it possible to cope with high-mix, variable-volume production. In this case, each functional device is tested at the module level and its operation? +t
The reliability of the product is improved because it is used after being repaired. By modularizing this function, large-scale systems can be easily completed, and costs can be reduced by mass production at the module level.
The key point is to significantly reduce the cost of the °ζ system by reducing assembly man-hours.

The following is known as a specific example of a communication method within an information centralized distributed processing system having the above-mentioned characteristics.

In other words, since many recent one-chip CPUs have a built-in serial port, this serial port is used to perform "ζ-fn". Here, the serial port is the following: say something

That is, FIG. 13 shows an example of an 8-bit serial port, in which (2) is an 8-bit shift register whose serial input terminal is connected to the serial input terminal SI of the CPU (20). Also, this shift register (
The serial output terminal of 21) is the latch circuit for IL-Soto (
22) and the CPU (2) via the output game 1- (23).
0) is connected to the serial output terminal SO.

Also, SCK is the clock terminal of CPtJ (20), and when the clock changeover switch (24) is switched to the terminal A side, the clock INGK from the internal clock generation source (25) in this CI) tJ (20) is This switch (
24) to the clock terminal of the shift register (21), and when the switch (24) is switched to the terminal B side, the clock EXCK input from the outside through the clock terminal SCK becomes the clock of the shift register (21). Supplied to the terminal.

Further, the parallel output terminal of the system 1-register (2) is connected to the internal data bus of the CPU (20).

The clock INCI (and IEXCK) has 8 bits, or 8 pulses, obtained during transmission. By supplying these 8 clock pulses to the system register (21), The 8-bit data is transferred to the serial output terminal SO via the latch circuit (22) and the output gate (23), and the 8-bit data input to the serial output terminal SL is transferred to this system register ( 21).

FIG. 14A shows a clock pulse supplied to this system register (21), FIG. 14B shows 8-bit data to be written, and FIG. 14C shows 8-bit data to be read. Data is read at the falling edge of the clock pulse, and data is written at the rising edge of the clock pulse.

The latch circuit (22) is used to hold one bit of read data when reading and writing in this way.

Then, when the counter (26) counts this shift clock pulse INCK or EXCK to 81,
An interrupt signal is obtained from this, whereby the data taken into the shift register (21) is read out and transferred to the internal data bus. Further, the next sending data is written into the shift register (21).

Communication within the information centralized distributed processing system described above is performed using a functional device equipped with a CPU having a serial port as described above. In other words, FIG. 30) serial output terminal SO of the slave functional device CPU (31) (32). connected to the serial input terminal SL of the board, and connected to the CPU (30
) serial input terminal SI of CPU (31) (3
2) respectively to the serial output terminal SO. In addition, the clock terminal SCK of the CPU (30) and the CPU (
'31) and (32) are connected to the clock terminal SCK. In this case, the clock selection switch (24) of the master CPU (30) is switched to the terminal A side, and the glue l cock selection switch (24) of the slave CPU (31) (32) is switched to the terminal ■3 side. Therefore, the ζ clock terminal SCK becomes an output terminal in the masked CPtJ (30), and becomes an input terminal in the slave CPUs (31) and (32).

Also, in this example, °ζ is the master's (: P U (
30) One pair of glue for the number of slave functional devices! ) Quest input terminal and output terminal are provided. In this example, since there are two slave functional devices, a request input terminal R (111), an output terminal RQOt, a request input terminal R (2) and an output terminal RQO2 are provided.

On the other hand, the slave CPU (31) (32) has
A pair of request input terminal RQI and output terminal RQO are each provided.

The request input terminals RQ11 and RQI2 of the master CPU (30) are connected to the slave CPU (30), respectively.
31) and (32) each request output terminal R
QO, the request output terminal RQOt and P port 02 of the master CPU (30) are connected to the request input terminal RQl of the slave CPUs (31) and (32), respectively.

Then, when the need for communication arises, for example when the mode changes in a VTR, a request is issued and communication is performed. For example, when the slave CPU (31) needs to communicate, the request output terminal RQO is used to communicate with the master CPU.
U (30) request input terminal RQ1. For example, the request signal supplied to the CPU (31) becomes "l", and the CPU (31)
Transmission from to CPU (30) is activated.

In response to this, the master CPU (30)
After the other work and other communication that U (30) is doing is completed, the master CPU (30)'s request output terminal 1? Slave CPU (31) from QO2
The request signal is supplied to the request input terminal RQI of the CPU (30) and the request signal is set to 11'', thereby activating transmission from the CPU (30) to the CPU (31).

Now, the slave CPU (31) and master CPU
Communication with (30) becomes disabled. And the CPU
Eight internal clocks INCK are obtained from (30), which are supplied to the built-in shift register (21) and sent to the slave's CP through the clock input/output terminal SCK.
ζ
The data read out by the leading edge of this clock pulse INCKO is supplied from the output terminal SO to the input terminal of the built-in shift register (21) through the input terminal SI of the other party, and at the trailing edge of the shift clock INCK,
Each is written into the shift register (21). In this way, data of the CPU (31) and data of the CPU (30:l) are simultaneously communicated, and the data of the CPU (30) and (31)
The data in the shift register (21) is, so to speak, replaced.

When this communication is finished, each CP receives an interrupt signal.
In U (30) and (31), shift register (21
), 8-bit parallel data is read out and supplied to the internal bus, and processing is performed according to the data.

During this communication, if there is another work request, such as a remote control interrupt request or a timer interrupt request, which should take priority over the communication, the request is stopped, that is, the request signal is set to 10'' and the communication is stopped. is interrupted and the routine for that interrupt is executed. At this time, the other party's C
The PU becomes aware of this based on the state of the request signal, considers the communication to be a failure, and restarts the communication after a while.

Note that the clock signal of the shift register (21) does not necessarily have to be output from the master CPU (30), and may be output from the slave CPU side.

[Problem that the invention seeks to solve]

In the case of the conventional communication methods described above, requests are issued only when communication is necessary, such as when the mode changes, and ζ communication is performed, so it is necessary to constantly monitor whether there are requests. In addition, as mentioned above, it is necessary to consider priorities with other work, and to
Communication management is difficult and bugs are likely to occur, as it is necessary to consider the priority order when communication requests from functional devices are bundled together. In addition, debugging is time consuming, which results in longer manufacturing times and more man-hours, making it difficult to design efficiently.

Furthermore, since communication is completed only once, there is also a drawback that if incorrect data is sent, the device will remain in the incorrect state until the next request is made.

[Means for solving problems]

Figure 1 shows an example of the basic configuration of this invention, in which there are five functional devices, and one of the functional devices has a CPU (4
0) is the master, CPUs (41) of other functional devices ~
(44) is the slave.

In this example as well, the serial output terminal SO of the master CPU (40) is connected to the serial input terminal S■ of the slave CPUs (41) to (44), and the serial input terminal S■ of the master CPU (40) is connected to the serial input terminal S■ are connected to the serial output terminals SO of the slave CPUs (41) to (44), respectively, and are further connected to the serial clock terminal SCK of the master CPU (40) and the slave CPU (44).
Serial clock terminals SCK of 1) to (44) are connected to each other.

And in this case, the master functional device's CPU (
40) respectively chip select signals C5, ~C34.
is the CPU (41) to (44) of each slave functional device.
) is supplied to the chip select terminal. In this case, the chip select signals C3i to C54 are signals whose phases are shifted so that the periods in which they are "0" do not coincide with each other in time, as shown in FIG. 2A to D. Also, E in the same figure shows the vertical synchronizing pulse VD from the horizontal and vertical synchronizing threads of the synchronizing signal processing system of this system, such as video information equipment, and the chip select signals C31 to C34 are synchronized with this vertical synchronizing pulse VD and have a vertical period. can get.

[Effect]

When the chip select signal C81 becomes IOJ, communication becomes possible between the master CPU (40) and the slave CPU (41), and during the period T1 when this signal C31 is 10'', the master CPU (40) or the slave CPU
The shift registers of each CPU (40) and (41) are clocked by clock pulses of the required number of bits from (41).
The stored data is transferred to the other party's shift register. In other words, simultaneous bidirectional communication is performed.

Next, in period T2 when the chip select signal C52 becomes 1 "0", communication becomes possible between the master CPU (40) and the slave CPU (42), and the chip select signal C33 becomes "0". In period T3, the master CPU (40) and slave CPU (
43), and furthermore, in period T4 when the chip select signal C34 becomes "0", the master 〇〇PU (40) and the slave CPU (44
), and each period T
Simultaneous bidirectional communication H is performed in the same manner as in 1.

Then, one set of the above periods T1 to T4 is repeated in a vertical period.

〔Example〕

Figure 3 shows an example of this invention, and this example is V
This is an example in which the present invention is applied to internal communication of a TR.

Further, in this example, the master functional device is a mode controller, which includes a CPU (50).

The slave functional devices are a tuner, a timer, and a mechanical controller, each of which has a CPU C (51), (52), and (53). These CPUs (50) to (53) are the first CPUs mentioned above.
Each has an 8-bit serial port as shown in Figure 3.

A vertical synchronizing pulse VD (Fig. 4A) is supplied to the CPU (50) of the mode controller via an input port, and communication is performed in vertical cycles in phase synchronization with this vertical synchronizing pulse VD as described later. It is designed to be

Serial output terminal SO of CPU (50) and CPU (51)
) to (53) are connected, and the serial input terminal S1 of the CPU (50) and the CPU
The serial output terminals SO of (51) to (53) are connected. Further, the serial clock terminals SCK of the CPUs (50) to (53) are connected to each other. In this example, the switch (2) of the master CPU (50) is similar to the previous example.
4) is terminal A side, slave CPU (51) to (53)
The switch (24) is switched to the terminal B side so that the clock is generated only from the master CPU (50).

Furthermore, chip select signals C81 to C53 are sent from the CPU (50) of the mode controller, which is the master functional device, to the CPU (50) of the tuner, timer, and mechanical controller, which are the functional devices of each slave.
1) to (53), and these CPUs (51) to
(53) and the CPU (50) can sequentially communicate with each other in time intervals. In other words,
The master CPU (50) manages communication, and
Communication is repeated periodically in phase synchronization with the vertical synchronization signal of the video signal.

The state of communication will now be explained in more detail.

That is, the chip select signal CSt (Figure 4B)
When the period TA is reached when the tuner becomes low level, the tuner's CP
Communication is now possible between U (51) and the CPU (50) of the mode controller, and as shown in Figure 4 E and F, the meat CPU
The output gates (23) of (50) and (51) are enabled and each outputs 8 bits of data DM (Fig. 4J).
and data DSt (K in the figure) are stored in each shift register (21). In this way, data DM,
When each DSt is used, 8
A fixed clock CLK (FIG. 4 I) is supplied to the built-in shift register (21), and is also supplied to the CPU (51) through the terminal SCK.
A clock CLK is supplied to the clock CLK. Therefore, the CPU (
The transmission data DM of the CPU (50) is taken into the shift register (21) of the CPU (51), and the transmission data DS□ of the CPU (51) is taken into the shift register (21) of the CPU (50). In this way, when the two-way simultaneous communication of word (8-bit) data is completed, the received data is read out in the form of parallel data and supplied to the internal bus, as shown in Figure 4 E and F. be done.

In this example, two words of data are communicated in one cycle between the mode controller and the tuner. Therefore, in the CPUs (50) and (51), the shift register (
21), and then eight clocks CLK (FIG. 1) are obtained again from the CPU (50), and two-way simultaneous communication of the second word data DM and DSL is performed.

When this second word communication is completed, both CPUs (50)
The serial ports (51) and (51) are disabled.

Examples of communication data between the mode controller and the tuner include output data of the tuner CPU (51) such as current channel display data on the display unit (511), channel position, band information, and tuning preset data. Tuner CPU input data includes a channel selection command and tuner CPLI (51) from another CPU.
) There is write request data to the non-volatile memory (512) connected to, for example, the last data of the speed mode β■, β■.

Next, when the chip select signal JF+C32 (Fig. 4C) reaches the low level period TB, the timer CPU (5
2) and the CPU (5jl) of the mode controller are now able to communicate, and as shown in Figure 4 E, G, I, J, and L, the data DM of the CPU (50) and the CPU
Bidirectional simultaneous communication with the data DS2 (52) is performed. In this example, the distance between these two CPUs (50) and (52) is 1
Communication is one word per cycle.

In this example, the timer CPLJ (52) receives a remote control signal from the remote control receiver (521) and drives the fluorescent display tube (522), so the timer's CPU
The output data of (52) includes remote control reception data, timer recording, power control data, etc., and the input data include counter value, V'
Data such as l'R function mode is listed.

Next, when the chip select signal CS3 (FIG. 4D) reaches the low level period TC, the CPU (53) of the mechanical controller and the CPU (50) of the mode controller
Communication is now possible between E and H in Figure 4.

Two-way simultaneous communication is performed between the data DM of the CPU (50) and the data DS3 of the CPU (53) in such a manner that the data I, J, and M are connected. In this example, communication between the two CPUs (50) and (53) is one word per period.

The mechanical controller receives information about the mode to which the mechanical deck (531) should transition next from the mode controller, and displays the current mode of the mechanical deck (531) and the counter display section (53).
2)" counter information, etc., to the CPU (5
The output data for 3) is information such as the counter value, the current mode and the next mode, or the status of 2-F, β■/β■, etc. in transition between the current mode and the next mode, and the input data is information about which mode to enter next. Data such as mode commands for what to do, status commands for commands such as β■/β■, and commands such as counter reset are listed.

As described above, since the signals C31 to C33 are signals synchronized with the vertical synchronization pulse, the period TA-TC specified by the chip select signals C5t to C33 is repeated in a vertical period in phase synchronization with the vertical synchronization pulse. , C.P.
Communication is periodically performed between U (50) and CPUs (51) to (53).

Then, the CPUs (51) to (53) of each slave
), other work is being done outside the communication interval TA-TC, so even if the above-mentioned periodic communication is performed, the other work will not be affected.

On the other hand, since the communication period is fixed, when doing other tasks in a time-sharing manner, it is possible to prevent one task from being interrupted due to communication, and the time can be easily managed. .

In addition, the master CPU (50) does not allocate the entire vertical cycle to internal communication, but instead provides a pause period and uses this pause period to perform external communication between this VTR and video camera and other peripheral devices, and other to do their job.

Note that in this case, the master CPU (50) may of course be used exclusively for communication.

The above is a case where each functional device is provided with a CPU having a serial port equipped with a shift register as shown in FIG. It is also possible to use one equipped with a serial boat.

It is also possible to use a CPU that does not have a serial port and is equipped with a shift register.

That is, when this CPU (60) is provided in a slave functional device, the serial output terminal SO of the master CPU, which has a serial port equipped with a shift register, is connected to the input capo I-(61) as shown in FIG. In addition, the serial input terminal SI and clock terminal SCK are connected to the output port (
62) and (63), respectively, and the chip select signal C8 is supplied to the interrupt input terminal INT. The selection signal C8 may be manually input through an input boat. Then, a signal is output from another output port (64) to enable the lines from the output ports (62) and (63), and this CPU (60)
A clock is created using software, and data is read and written bit by bit using software. A clock created by this software is supplied to the master CPU, and this is used as the shift clock for its built-in shift register. That is, the clock selection switch of the master CPU is connected to the terminal B side.

In addition, when using a CA PU that does not have such a shift register on the master functional device side, the sixth
As shown in the figure, the output port (71) is the serial output terminal SO, and the human capo-1- (72) is the serial input terminal S.
r, and the output port (73) is the clock output terminal SCK.
, the output port (74) is used as the output terminal for the chip select signal, and in this case as well, a clock is created using software and transmitted to the slave CPU side, and the master CPU reads and writes data bit by bit using software.

In addition, especially when processing a large amount of data, as shown in FIG. are provided, and the CPUs of these slave devices (80) (90
), as shown in FIG. 7, the CPU (70) of the master functional device and the CPU (80) of the slave functional device connected via a serial path line. Set up two serial boats in
As shown in Figure 8, by time division multiplexing, the master CPU
Communication between the slave CPUs (80) and (90) may be performed during a pause period of communication between the slave CPUs (70) and the slave CPUs (80).

Furthermore, if the slave CPU (80) has only one serial port, a switch (100) is provided on the serial bus as shown in FIG.
0) and the slave CPU (80), the slave CPU (80) and the master CPU (70)
The communication path with the slave CPUs (80) and (90
) can be connected to the communication path.

Furthermore, there are CPUs that do not have an 8-bit shift register as described above but are equipped with a serial port that has a 4-bit shift register;
When using this for communication with a CPU that has an 8-bit serial port, the 4-bit clock is issued twice from the CPU side that has this 4-bit serial port, taking into account the time it takes to import data into the internal bus. This allows communication to occur without any problems.

In addition, the clock is the master's CP LJ or the slave's C
Instead of creating it on the PU, it is better to use one created on another CPU or hardware in common. At this time, a clock generation timing signal is sent from the master CPU to this clock generation means.

available.

The above explanation has been given using communication between functional devices inside a VTR as an example, but it is not limited to internal communication of such a single electronic device. When considered, it goes without saying that the present invention can also be applied to communication between a VTR and a video camera, a VTR and a monitor receiver, etc. within this system.

(Effects of the Invention) According to the present invention, in addition to the above-mentioned information pot 11, there are general effects of communication within the processing system, namely, reduction of manufacturing man-hours by reducing the number of bins, and facilitating M recognition. In addition to the benefits of high serviceability and the ability to streamline multi-product, variable-volume production through functional modularization, the following benefits are achieved by making communication cyclical in synchronization with the synchronization signal of the synchronization system. .

That is, by making the communication periodic, even if an erroneous communication occurs, the correct data is immediately sent and the normal state is restored, which reduces the error rate and improves reliability. Furthermore, since the communication is periodic and communication is managed only on the master side, communication management is very easy, and communication bugs can be easily debugged.

Further, since the communication is periodic communication that is phase-synchronized with the synchronization signal of the synchronization thread of the system, processing can be easily performed based on information that performs processing in synchronization with this synchronization signal. For example, when editing on a VTR, the command data is phase-synchronized with the vertical sync pulse, so it is possible to accurately judge how far in the future the signal should be connected. In addition, it becomes easier to communicate between frames and fields using time codes as communication data.

[Brief explanation of drawings]

FIG. 1 is a block diagram of an example of the basic configuration of this invention, FIG. 2 is a diagram for explaining the same, FIG. 3 is a block diagram of an embodiment of this invention, and FIG. Figures 5 and 6 are explanatory diagrams showing other examples of serial ports, and Figures 7 to 9 are diagrams showing the slave functional devices when there are additional slave functional devices. A diagram for explaining an example of a communication method between both devices, FIG. 10~
FIG. 12 is a diagram showing an example of the processing method of various functions of the system,
FIG. 13 is a block diagram of an example of a serial port, FIG. 14 is a diagram for explaining the same, and FIG. 15 is a diagram of an example of a communication system using this serial port. (40) is the CPU of the master functional device. (41) to (44) are CPUs of slave functional devices
, So is a serial output terminal, St is a serial input terminal,
SCK is a serial clock terminal. JP-A-1-166244 (10) Figure 14 Figure 15

Claims (1)

[Claims] In a system that has multiple functional devices each having a serial input terminal, a serial output terminal, and a clock terminal, and a synchronous signal processing system, one of the multiple functional devices is a master, the others are slaves, and the serial input of the master functional device is terminal and the serial output terminal of each slave's functional device, the serial output terminal of the master's functional device above and the serial input terminal of each slave's functional device, the clock terminal of the above master's functional device and the clock terminal of each slave's functional device. At the same time, a chip select signal is supplied from the master's functional device to each slave's functional device, and this chip select signal causes communication between the master's functional device and each slave's functional device to be exclusively sequential. an intra-system communication method that is performed periodically in synchronization with the synchronization signal.