CN114124609A - Communication device and communication method based on 1553B bus - Google Patents

Abstract

The invention discloses a communication device and a communication method based on a 1553B bus, wherein the device comprises the following components: the dual-channel transceiver links to each other with SOC control assembly and transformer respectively, dual-channel transceiver and outside 1553B data bus coupling connection, the transformer passes through level conversion circuit and is connected to the coupler, and the coupler is connected with outside 1553B data bus, outside 1553B data bus passes through dual-channel transceiver and communication equipment and connects, SOC control assembly is used for controlling dual-channel transceiver and communication equipment and communicates.

Description

Communication device and communication method based on 1553B bus

Technical Field

The invention relates to the technical field of aviation and aerospace electronics integration, in particular to a 1553B bus-based communication device and a 1553B bus-based communication method.

Background

The statements in this section merely provide background information related to the present disclosure and may not necessarily constitute prior art.

In the prior art, a 1553B data bus remote terminal and a bus monitor multifunctional device are independent devices generally, and few devices with two-in-one functions exist. The design schemes of an independent remote terminal and bus monitor multifunctional equipment are generally two, one scheme is that a 1553B interface chip and a CPU are used, the 1553B interface chip is typical like MC61580, the CPU selects a 16-bit singlechip or an ARM controller matched with the CPU, the MC61580 completes Manchester coding and analysis of a 1553B transmission protocol, and the CPU realizes interface control of the MC61580 chip and data moving work; the other is that an FPGA + transceiver architecture is used, the transceiver realizes Manchester coding conversion, and the FPGA compiles complex logic to realize functions of deserializing, shift output, serial-parallel conversion, mode control, protocol analysis, data transmission and the like of 1553 bus data.

The prior art can not meet the requirement that the same product simultaneously integrates the functions of a remote terminal and a bus monitor, can not switch working modes in use, and has the defects that the user-defined protocol function is difficult to change quickly and the flexibility is insufficient.

Disclosure of Invention

In order to solve the problems, the invention discloses a communication device and a communication method based on a 1553B bus, which can simultaneously realize the functions of a remote terminal and a bus monitor, can switch and select working modes in use, and can flexibly realize a user-defined protocol through software updating.

In some embodiments, the following technical scheme is adopted:

a 1553B bus-based communication device, comprising: a two-way transceiver, an SOC controller assembly, and a transformer;

the dual-channel transceiver links to each other with SOC control assembly and transformer respectively, dual-channel transceiver and outside 1553B data bus coupling connection, the transformer passes through level conversion circuit and is connected to the coupler, and the coupler is connected with outside 1553B data bus, outside 1553B data bus passes through dual-channel transceiver and communication equipment and connects, SOC control assembly is used for controlling dual-channel transceiver and communication equipment and communicates.

According to the technical scheme, the SOC controller component comprises a main control chip, the main control chip adopts an SOC system on chip, the SOC system on chip comprises an FPGA and a hard core processor, and data communication is carried out between the FPGA and the hard core processor through an internal AXI bus.

According to a further technical scheme, the external 1553B bus comprises an A channel and a B channel, logic of the FPGA corresponds to the A channel and the B channel of the 1553B, the FPGA comprises two sets of same logic conversion modules, and each logic conversion module comprises a single-end and double-end conversion module, a coding module and a decoding module.

According to a further technical scheme, the 1553B bus interface module comprises a register updating module, a reading and writing module and an idle judging module, the bus interface module is respectively connected with an AXI bus and an encoding and decoding module, and the register comprises an interrupt register, a state register and a data register;

the register updating module is used for updating the value of the status register according to the receiving/sending status identifier, updating the value of the interrupt register according to the validity of the decoding data and the sending completion flag, and generating an interrupt signal;

the read-write module is used for executing read-write operation of receiving FIFO and transmitting FIFO according to read-write pulse on a 1553B bus;

the idle judging module is used for timing the idle time of the bus, generating idle interruption and judging the information of the bus monitor by the protocol layer.

According to the further technical scheme, an operating system is embedded in the hard-core processor, the operating system mounts the 1553B bus as character equipment through a driving module, interface communication between a user side and the 1553B bus is achieved, and the driving module comprises an initialization module, an interrupt processing module and a bus monitor message judgment task module.

According to the further technical scheme, the two-way transceiver is connected to the 1553B bus through the single-end and double-end conversion module, the biphase Manchester codes are converted into single-end signals through the coding module when the two-way transceiver receives the signals, and the single-end signals are converted into double-end signals through the decoding module when the two-way transceiver sends the signals.

According to the technical scheme, the decoding module comprises a synchronous head identification module, a serial-parallel conversion module and a check module, the synchronous head identification module is used for judging whether an instruction/state word or a data word is included according to a synchronous head of input data, the serial-parallel conversion module is used for performing serial-parallel conversion on the input data according to a clock module input clock, the check module is used for performing parity check on the input data, the coding module receives data from a 1553B bus interface module, the FPGA is used for adding the corresponding synchronous head, performing check and calculation, performing serial-parallel conversion on the output serial data to the single-end and double-end conversion module, and giving a finished state identifier after the transmission is finished.

In other embodiments, the following technical solutions are adopted:

A1553B bus-based communication method comprises an interrupt processing,

the interrupt processing specifically includes:

reading data received by a bus;

carrying out mode judgment, and if the bus monitor is in a monitoring mode, carrying out interruption mode judgment;

if the interruption mode is receiving interruption, storing the data into the ring buffer, and if the interruption mode is sending interruption, storing the data in the sending buffer area into the ring buffer; and if the interrupt mode is idle interrupt, storing an idle interrupt identifier word.

If the bus monitor mode is the bus monitor monitoring mode, if the bus monitor mode is the remote terminal mode, the command word judgment is carried out, and data is written into the FIFO.

In a further technical solution, the command word determining process includes:

if the command word is the command word, analyzing the command word, filtering the RT address, judging the transmission or the reception, writing the data into FIFO, and simultaneously storing the data word;

if not, judging whether the data word is received completely, if so, returning to continuously judge whether the data word is the command word, otherwise, storing the data word.

The technical scheme further comprises bus monitor message judgment, wherein the bus monitor message judgment process comprises the following steps:

waiting for BM ring buffer semaphore;

reading data, judging an idle interrupt mark, if the idle interrupt exists, giving a message overtime mark, writing the message overtime mark into a message queue, and continuously waiting for the signal quantity of the BM circular buffer area;

if the command is not the idle interrupt, judging the command or the response word, judging whether the command is a new command, if so, waiting to receive data or respond according to the new command, otherwise, continuing to wait to receive the next data until the message reception or the response is finished, and writing the message into a queue.

Compared with the prior art, the invention has the beneficial effects that:

the method can realize the functions of the remote terminal and the bus monitor simultaneously by being based on the 1553B bus, can switch and select the working modes in the communication process, and can customize the protocol function by a user to realize quick change for the user to flexibly set.

Drawings

Fig. 1 is a schematic diagram illustrating an overall structure of a 1553B bus-based communication device according to an embodiment of the invention;

fig. 2 is a block diagram of external 1553B bus devices and FPGA logic functions according to an embodiment of the present invention;

FIG. 3 is a diagram of a driving module according to an embodiment of the present invention;

FIG. 4 is a flowchart illustrating a second interrupt processing module according to an embodiment of the present invention;

fig. 5 is a flow chart of a BM message determination task in the second embodiment of the present invention.

Detailed Description

It should be noted that the following detailed description is exemplary and is intended to provide further explanation of the disclosure. Unless defined otherwise, all technical and scientific terms used herein have the same meaning as commonly understood by one of ordinary skill in the art to which this application belongs.

It is noted that the terminology used herein is for the purpose of describing particular embodiments only and is not intended to be limiting of example embodiments according to the present application. As used herein, the singular forms "a", "an" and "the" are intended to include the plural forms as well, and it should be understood that when the terms "comprises" and/or "comprising" are used in this specification, they specify the presence of stated features, steps, operations, devices, components, and/or combinations thereof, unless the context clearly indicates otherwise.

The embodiments and features of the embodiments of the present invention may be combined with each other without conflict.

Interpretation of terms:

the 1553B data bus is totally called as an airplane internal time-sharing instruction/response multiplex transmission data bus, the bus is provided with three data types, namely a Bus Controller (BC), a Remote Terminal (RT) and a Bus Monitor (BM), the bus is only provided with one BC, but the bus is allowed to switch the BC, the RT or the BM can be up to 31, and the data transmission types comprise BC-RT, RT-BC, RT-RT and the like. The basic unit of the message transmitted on the bus is a word, each word is 20 bits in length, the message comprises an instruction word, a response word and a data word, each message always starts with the instruction word and comprises a plurality of data words, and partial message types need RT (reverse transcription) to return the response word. The bus has double redundancy, and has the characteristics of high reliability, strong real-time performance and the like.

Example one

In one or more embodiments, a 1553B bus-based communication device is disclosed, and fig. 1 is a schematic diagram of an overall structure of the 1553B bus-based communication device, where:

the method comprises the following steps: a two-way transceiver, a transformer, an SOC controller assembly, and a power circuit;

the dual-channel transceiver links to each other with SOC control assembly and transformer respectively, dual-channel transceiver and outside 1553B data bus coupling connection, the transformer passes through level conversion circuit and is connected to the coupler, and the coupler is connected with outside 1553B data bus, outside 1553B data bus one end is connected with bus controller, and the other end and 1553B communication equipment are connected, bus controller passes through dual-channel transceiver and communication equipment connects, SOC control assembly is used for controlling dual-channel transceiver and communication equipment and communicates.

The communication equipment can only work in a certain receiving or transmitting state and is half-duplex communication.

Specifically, the communication device includes a Remote Terminal (RT) and a Bus Monitor (BM).

The dual-channel transceiver is used for receiving signals or sending signals to realize half-duplex communication, and the SOC control assembly is used for controlling the dual-channel transceiver to receive signals or send signals to realize the functions of a Remote Terminal (RT) and a Bus Monitor (BM).

The SOC controller is based on CYCLONE V, is composed of an FPGA programmable logic and an HPS hard-core processor, is connected with the two-way transceiver, and completes RT and BM functions of a 1553B data bus through logic and programs.

The power supply circuit is connected with the power supply monitoring circuit, the two-way transceiver and the SOC controller component through the power supply protection circuit; the power circuit comprises a main power supply and a standby power supply, wherein the main power supply and the standby power supply are isolated from each other and are both direct current 28V; the power supply circuit preferentially uses a main power supply, if the main power supply fails, a standby power supply is used as an input, and 5V, 3.3V, 2.5V and 1.1V power supplies are output after DC-DC conversion. The power supply circuit has protection and monitoring functions, the protection circuit comprises overvoltage protection, overcurrent protection, overheat protection and the like, and the monitoring circuit can provide power-on and power-off indication signals.

The SOC controller component comprises a main control chip, a DDR3, an eMMC, a clock and other external circuits;

the main control chip adopts an SOC (system on chip) which comprises an FPGA (field programmable gate array) and a hard core processor (HPS). The FPGA and a hard core processor (HPS) are in data communication through an internal AXI bus, the bus is bidirectional, all bridges are compatible with AXI-3/4 and support simultaneous read-write operation, similarly, a bus host in the FPGA architecture can access the HPS bus and peripheral equipment thereof through the bridge connection from the FPGA to the HPS, and the HPS comprises a driving module which is used for controlling the communication of a bus interface module. Specifically, the main control chip and the two-way transceiver controller may be selected according to the actual technical situation in the field, for example, the main control chip may be a cycleev chip; the two-way transceiver controller adopts a single-chip two-way transceiver HI1573 chip of holt corporation.

The DDR3 is a system operation memory and can provide high-speed instruction and data moving capacity for the system; the eMMC provides storage space for system logic, binary instruction codes and system operation parameters, and can be used as user data storage.

The transformer is connected to the bus through a coupler, and the coupling method adopts the following steps: 1.79 transformer ratio to facilitate connection to the 1553B bus via standard couplers.

Fig. 2 is a block diagram of an external 1553B bus device and an FPGA logic function module, as shown in fig. 2, the external 1553B bus includes two channels a and B, the FPGA logic corresponds to the channels a and B of 1553B, the FPGA includes two sets of the same FPGA including two sets of the same logic conversion modules, and the logic conversion modules include: the device comprises a clock module, a single-end and double-end transformation module, an encoding module, a decoding module, a fifo module and an avalon interface module.

The single-double end conversion module is connected with the double-channel transceiver and is hung to the 1553B bus through the single-double end conversion module, the double-channel transceiver converts biphase Manchester codes into single-end signals through the coding module when receiving signals, and converts the single-end signals into double-end signals through the decoding module when sending the signals.

The decoding module comprises a synchronous head identification module, a serial-parallel conversion module and a check module, wherein the serial-parallel conversion module is used for performing serial-parallel conversion on input data according to an input clock of the clock module, the synchronous head identification module is used for judging whether the input data is an instruction/state word or a data word according to a synchronous head of the input data, the check module is used for performing parity check on the input data and giving out data, a Command State Word (CSW), a Data Word (DW) mark and a check error mark, the coding module is used for receiving starting transmission, the CSW/DW mark and FIFO data from the 1553B bus interface module, the FPGA is used for adding the corresponding synchronous head, checking and calculating, performing serial-parallel conversion and outputting serial data to the single-end and double-end conversion module, and giving out a completion state mark after transmission is completed.

The bus interface module comprises a register updating module, a reading and writing module and an idle judging module, the bus interface module is respectively connected with the AXI bus and the coding and decoding module, and the register comprises an interrupt register, a state register and a data register;

the read-write module is used for executing read-write operation of a first-in first-out (FIFO) receiving memory and a FIFO transmitting memory according to read-write pulses on a 1553B bus, and the register updating module is used for updating a state register value according to a receiving/transmitting state identifier, updating an interrupt register value according to decoding data validity and a transmitting completion flag, and generating an interrupt signal at the same time. The idle judging module is used for timing the idle time of the bus, generating idle interruption and judging the information of the Bus Monitor (BM) by the driving program.

The clock module generates an encoding clock and a decoding clock respectively after the input clock passes through the PLL, and specifically, the decoding clock is 4 times of the encoding clock.

The interrupt comprises receiving interrupt, sending completion interrupt and bus idle interrupt; the hardware-core processor (HPS) is embedded with a real-time operating system, the operating system mounts a 1553B bus into character equipment through a driving module to realize a user application program interaction interface between a user side and the 1553B bus, and the core of the hardware-core processor (HPS) is ARM Cortex-A9.

As shown in fig. 3, the driving module includes an initialization module, an interrupt processing module, an IO control module, and a BM message determination task module.

The initialization module comprises an initialization device descriptor, an initialization device member parameter, memory allocation, hooking interruption, addition of an IO system read-write and control function interface, device creation, BM message judgment task creation and the like.

The interrupt processing module comprises an interrupt identification and protocol processing module, and the interrupt identification respectively executes receiving, sending and idle interrupt operation according to the value of the read interrupt register; the protocol processing performs response operations of data storage to corresponding ring buffers and local Remote Terminals (RT) according to 1553B protocol.

The IO control module provides an application interface for a user side, and the interface provides a user operation interface such as an RT address setting interface, a sub-address data setting interface, an RT, BM and dual-function change mode interface, RT data reading, BM message reading and the like;

and judging data received by a bus read from the buffer, judging whether the data is an instruction/state word or a data word according to the value of the state register, performing integrity reading on the message according to the definition of each field of the instruction word in the 1553B protocol, combining the message, giving a mark of the message type and whether the message is correct, and writing the message into a message queue after the completion.

Example two

In one or more embodiments, a 1553B bus-based communication method is disclosed, comprising an interrupt processing;

fig. 4 is a flowchart illustrating the operation of the interrupt processing module, and fig. 4 illustrates the following steps:

reading data received by a bus, wherein the data is a working mode register value set by a user;

judging a mode, if the mode is a Bus Monitor (BM) monitoring mode, judging an interrupt mode, and performing corresponding storage processing according to the interrupt mode;

the corresponding processing according to the interrupt mode comprises the following steps: if the interruption mode is receiving interruption, storing the data into the ring buffer, and if the interruption mode is sending interruption, storing the data in the sending buffer area into the ring buffer; and if the interrupt mode is idle interrupt, storing an idle interrupt identifier word.

If the bus monitor is in the monitoring mode, if the bus monitor is in the Remote Terminal (RT) mode, judging command words, and writing data into FIFO;

the command word judgment process includes:

if the command word is the command word, analyzing the command word, filtering the RT address, judging the transmission or the reception, writing the data into FIFO, and simultaneously storing the data word;

if not, judging whether the data word is received completely, if so, returning to continuously judge whether the data word is the command word, otherwise, storing the data word.

The mode judgment comprises judging whether the command/state word or the data word is the command/state word or the data word according to the value of the state register, performing integrity reading of the message according to the definition of each field of the command word in the 1553B protocol, performing message combination, giving a mark of the message type and the message correctness, and writing the mark into a message queue after the completion.

Fig. 5 is a BM message determining task module, which specifically includes the following steps as shown in fig. 5:

waiting for BM ring buffer semaphore;

reading data, judging an idle interrupt mark, if the idle interrupt exists, giving a message overtime mark, writing the message overtime mark into a message queue, and continuously waiting for the signal quantity of the BM circular buffer area;

if the command is not the idle interrupt, judging the command or the response word, judging whether the command is a new command, if so, waiting to receive data or respond according to the new command, otherwise, continuing to wait to receive the next data until the message reception or the response is finished, and writing the message into a queue.

Although the embodiments of the present invention have been described with reference to the accompanying drawings, it is not intended to limit the scope of the present invention, and it should be understood by those skilled in the art that various modifications and variations can be made without inventive efforts by those skilled in the art based on the technical solution of the present invention.

Claims (10)

1. A 1553B bus-based communication device, comprising: the dual-channel transceiver, SOC controller subassembly and transformer, its characterized in that, the dual-channel transceiver links to each other with SOC control subassembly and transformer respectively, the dual-channel transceiver is connected with outside 1553B data bus coupling, the transformer passes through level conversion circuit and is connected to the coupler, and the coupler is connected with outside 1553B data bus, outside 1553B data bus passes through the dual-channel transceiver and is connected with communication equipment, the SOC control subassembly is used for controlling dual-channel transceiver and communication equipment and communicates.

2. The 1553B bus-based communication device of claim 1, wherein the SOC controller component comprises a master control chip, the master control chip adopts an SOC system on chip, the SOC system on chip comprises an FPGA and a hard-core processor, data communication is performed between the FPGA and the hard-core processor through an internal AXI bus, and the hard-core processor comprises a driving module, and the driving module is used for controlling the 1553B bus interface module.

3. The 1553B bus-based communication device according to claim 1, wherein the external 1553B bus comprises an A channel and a B channel, logic of the FPGA corresponds to the A channel and the B channel of the 1553B, the FPGA comprises two sets of same logic conversion modules, and the logic conversion modules comprise a single-end and double-end transformation module, an encoding module and a decoding module.

4. The communication device according to claim 2, wherein the 1553B bus interface module comprises a register update module, a read/write module and an idle determination module, the bus interface module is respectively connected to the AXI bus and the codec module, and the register comprises an interrupt register, a status register and a data register;

the register updating module is used for updating the value of the status register according to the receiving/sending status identifier, updating the value of the interrupt register according to the validity of the decoding data and the sending completion flag, and generating an interrupt signal;

the read-write module is used for executing read-write operation of receiving FIFO and transmitting FIFO according to read-write pulse on a 1553B bus;

the idle judging module is used for timing the idle time of the bus, generating idle interruption and judging the information of the bus monitor by the protocol layer.

5. The communication device based on the 1553B bus as claimed in claim 2, wherein an operating system is embedded in the hard core processor, the operating system mounts the 1553B bus as a character device through a driving module to realize interface communication between a user side and the 1553B bus, and the driving module comprises an initialization module, an interrupt processing module and a bus monitor message judgment task module.

6. The communication device according to claim 3, wherein the dual-channel transceiver is connected to the 1553B bus through the single-end and dual-end conversion module, the bi-phase Manchester coding is converted into a single-end signal through the coding module when the signal is received by the dual-channel transceiver, and the single-end signal is converted into a dual-end signal through the decoding module when the signal is transmitted.

7. The 1553B bus-based communication device as claimed in claim 3, wherein the decoding module comprises a synchronization header identification module, a serial-to-parallel conversion module and a check module, the synchronization header identification module is used for judging whether the input data is an instruction/state word or a data word according to a synchronization header of the input data, the serial-to-parallel conversion module is used for performing serial-to-parallel conversion on the input data according to a clock module input clock, the check module is used for performing parity check on the input data, the coding module receives data from the 1553B bus interface module, the FPGA is used for adding a corresponding synchronization header, performing check and calculation, performing serial-to-serial conversion on the output serial data to the single-end and double-end conversion module, and giving a completion state identifier after transmission is completed.

8. A communication method based on a 1553B bus comprises interrupt processing, and is characterized in that the interrupt processing specifically comprises the following steps:

reading data received by a bus;

carrying out mode judgment, and if the bus monitor is in a monitoring mode, carrying out interruption mode judgment;

if the interruption mode is receiving interruption, storing the data into the ring buffer, and if the interruption mode is sending interruption, storing the data in the sending buffer area into the ring buffer; if the interruption mode is idle interruption, storing an idle interruption identifier word;

if the bus monitor mode is the bus monitor monitoring mode, if the bus monitor mode is the remote terminal mode, the command word judgment is carried out, and data is written into the FIFO.

9. The 1553B bus-based communication method of claim 8, wherein the command word judgment process comprises:

if the command word is the command word, analyzing the command word, filtering the RT address, judging the transmission or the reception, writing the data into FIFO, and simultaneously storing the data word;

if not, judging whether the data word is received completely, if so, returning to continuously judge whether the data word is the command word, otherwise, storing the data word.

10. The 1553B bus-based communication method according to claim 8, further comprising a bus monitor message judgment process, wherein the bus monitor message judgment process comprises the following steps:

waiting for BM ring buffer semaphore;

reading data, judging an idle interrupt mark, if the idle interrupt exists, giving a message overtime mark, writing the message overtime mark into a message queue, and continuously waiting for the signal quantity of the BM circular buffer area;

if the command is not the idle interrupt, judging the command or the response word, judging whether the command is a new command, if so, waiting to receive data or respond according to the new command, otherwise, continuing to wait to receive the next data until the message reception or the response is finished, and writing the message into a queue.

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