JP2001195356A - Communication control circuit - Google Patents

Abstract

PROBLEM TO BE SOLVED: To solve the problems that the loads of a CPU become heavy and data transmission and reception can not be efficiently executed since the CPU controls clock line changeover based on interruption request signals generated by clock changeover. SOLUTION: A pulse edge detection circuit 1 detects the level of a first clock SCK1 on a first clock line 11 and generates a one-shot pulse P when the level is changed. A changeover register 2 changes a setting value when the one-shot pulse P is inputted. A selector 3 switches connection to the first clock line corresponding to the setting value of the changeover register 2 without the intervention of the CPU. A communication control timing generation circuit 4 controls the data transmission and reception in synchronism with the first clock SCK1 obtained through the switched first clock line 11.

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention automatically switches clocks when detecting a change in the level of a plurality of communication clocks transmitted and supplied via a clock line, and transmits and receives data in synchronization with the switched clocks. The present invention relates to a communication control circuit for performing control.

[0002]

2. Description of the Related Art In a conventional communication control circuit, a plurality of communication clocks transmitted through a clock line are input, and data transmission and reception are controlled in synchronization with the input communication clock (hereinafter referred to as a clock). When switching the clock, an interrupt request signal is generated, a CPU (not shown) executes a predetermined instruction, selects a clock line, and switches the clock. Therefore, when multiple interrupt requests with higher priority are generated in comparison with the priority of the interrupt request generated based on the clock switching request, the load of the CPU executing the instruction becomes heavy, and the clock switching is performed. The interrupt request processing based on the request is delayed, so that the clock switching cannot be executed promptly, and the transmission and reception of serial data synchronized with the clock may not be executed.

FIG. 6 is a block diagram showing a conventional communication control circuit. In FIG. 6, reference numeral 61 denotes a pulse edge detection circuit for detecting a level change of the first clock SCK1 to generate a one-shot pulse, 62 a switching register, 63 is a selector, 64 is a communication control timing generation circuit, 65 is an 8-bit data shift register, 66 is an address control circuit, 67 is an internal address bus, 68 is an internal data bus,
70 is a memory such as a RAM, 71 is a first clock line,
72 is a second clock line, 73 is a data line, 74
Is a pulse edge detection flag. A master device 69 supplies the first clock SCK1 and the second clock SCK2 to the communication control circuit 400 via the first clock line 71 and the second clock line 72.

A conventional communication control circuit 400 includes a pulse edge detection circuit 61, a switching register 62, a selector 63,
Communication control timing generation circuit 64, data shift register 65, address control circuit 66, internal address bus 6
7, internal data bus 68, pulse edge detection flag 7
4 and a memory 70.

Next, the operation will be described. FIG. 7 is a timing chart showing the clock switching operation of the conventional communication control circuit 400 shown in FIG. The conventional communication control circuit 400 includes two clock lines for transmitting a first clock SCK1 and a second clock SCK2, that is, a first clock line 71 and a second clock line 72, and a data line for transmitting and receiving data. It is connected to the master device 69 via 73. In the following description, the case where the number of clock lines is two and the data length of serial transmission / reception is 8 bits will be described.

The switching register 62 of the communication control circuit 400
In the field, address information indicating the address of the second clock line 72, specifically, an L level value indicating the second clock line 72 is set as an initial value.

The communication control timing generation circuit 64 includes a control register (not shown) therein, and stores control data for controlling various control signals required for communication. When serially transmitting data to the master device 69 via the data line 73, a CPU (not shown) executes an instruction and the address control circuit 66 performs data shift based on address data on the internal address bus 67. By specifying the register 65, via the internal data bus 68,
Data is written into the data shift register 65.
Since an L level value for selecting the second clock line 72 is set in the switching register 62, the selector 6
Reference numeral 3 connects the second clock line 72 to the communication control timing generation circuit 64.

Then, as shown in the timing chart of FIG. 7, a pulse of the second clock SCK2 is supplied to the communication control timing generation circuit 64 via the second clock line 72, and the pulse is supplied to the rising edge of the pulse of the second clock SCK2. Synchronously, 8-bit serial data DA7 (M
SB), DA6,. . . , DA1, DA0 (LSB)
Is serially transmitted to the master device 69 via the data line 73 (timing T71 to T72). In this case, the transmitted data is MSB first.

Next, when the first clock SCK1 holding the H level falls to the L level (at timing T7).
3) The pulse edge detection circuit 61 connected to the first clock line 71 detects the falling edge of the first clock SCK1 (timing T73), and outputs 1 in synchronization with the falling edge of the first clock SCK1. Generates and outputs shot pulses.

When a one-shot pulse is output from the pulse edge detection circuit 61 (timing T73), a detection flag is set in the pulse edge detection flag 74.
At the same time, one shot pulse is used as an interrupt request signal
Output to PU (not shown).

When the CPU receives the interrupt request signal output from the pulse edge detection circuit 61, it executes an interrupt program routine. As a result, the pulse edge detection flag 74 is checked, and the pulse edge detection circuit 61
When it is confirmed that a one-shot pulse has been output from, an H level value is written into the switching register 62 so that the selector 63 selects the first clock line 71. The selector 63 selects the first clock line 71 according to the H level value set in the switching register 62, and connects the first clock line 71 to the communication control timing generation circuit 64. Thereby, the pulse of the first clock SCK1 is output to the communication control timing generation circuit 64.
It can be supplied to

Next, based on the address obtained via the internal address bus 67, the address control circuit 66 specifies the data shift register 65. Thereafter, data to be transmitted is stored in the data shift register 65 via the internal data bus 68, and the pulse of the first clock SCK1 is transmitted from the master device 69 to the first clock line 71.
To the communication control timing generation circuit 64 via Then, in synchronization with the rising edge of the pulse of the first clock SCK1 (timing T75), the transmission data stored in the data shift register 65 is serially transmitted to the master device 69 via the data line 73 ( Timings T75 to T76).

[0013]

Since the conventional communication control circuit is configured as described above, when data transmission / reception is controlled in synchronization with the switched clock, it is generated in response to a clock switching request. The CPU executes an instruction related to data transmission / reception based on the interrupt request signal to transmit / receive data. Therefore, compared with the priority of the interrupt request signal generated based on the clock switching request,
If an interrupt with a higher priority occurs, or if an interrupt request signal occurs frequently due to frequent clock switching requests, the load of executing the CPU instruction becomes heavy, and the processing of the interrupt request signal is delayed. In addition, there has been a problem that clock switching cannot be performed quickly and data transmission and reception cannot be performed efficiently.

SUMMARY OF THE INVENTION The present invention has been made to solve the above problems, and senses the state of a plurality of clock lines for supplying a plurality of communication clocks, so that the clocks can be automatically transmitted without CPU intervention. It is an object of the present invention to provide a communication control circuit capable of efficiently controlling data transmission and reception in synchronization with the switched clock.

[0015]

A communication control circuit according to the present invention includes a pulse edge detection circuit, connection means, and control means. The pulse edge detection circuit is connected to a plurality of clock lines that supply a plurality of clocks other than the n-th clock line that supplies the n-th clock, detects a level of the plurality of clocks, and responds to a clock that has caused a level change. The generated one-shot pulse is generated and output. The connection means is connected to the n-th clock line in an initial state, and switches the connection to the clock line corresponding to the clock having the level change when the one-shot pulse is input. The control means controls the transmission and reception of data in synchronization with the pulse of the n-th clock in the initial state, and is supplied via the clock line connected by the connection means when the one-shot pulse is input. By controlling the data transmission and reception in synchronization with the clock pulse, the clock is automatically switched without the intervention of the CPU, and the data is transmitted and received in synchronization with the switched clock.

The communication control circuit according to the present invention counts the pulse of the n-th clock which is always supplied via the n-th clock line, and generates and outputs an overflow signal when the counted number reaches a predetermined value. There is further provided a counting means for setting the count number to an initial value when the one-shot pulse output from the edge detection circuit is input. Then, when the overflow signal output from the counting means is input in a state where the clock lines other than the n-th clock line are connected, the connecting means switches the connection to the n-th clock line, and It is characterized in that n clocks are supplied to the control means.

In the communication control circuit according to the present invention, the pulse edge detection circuit includes a register, stores a value corresponding to a level change of a plurality of clocks other than the n-th clock, and decodes the value stored in the register. The information processing apparatus further includes a decoder, and the connection means switches connection of the clock line according to a decoding result output from the decoder.

[0018]

DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS One embodiment of the present invention will be described below. Embodiment 1 FIG. FIG. 1 is a block diagram showing a communication control circuit according to Embodiment 1 of the present invention. In FIG. 1, reference numeral 1 denotes a level change of a first clock SCK1 supplied via a first clock line 11, A pulse edge detection circuit that generates and outputs a one-shot pulse when a change is detected, and a switching register that stores a set value for selecting and switching a clock line according to the one-shot pulse output from the pulse edge detection circuit 1 (Connecting means) 3 is a selector (connecting means) for selecting one of the first clock line 11 and the second clock line 12 according to the set value set in the switching register 2.
It is. In the switching register 2, as an initial value,
A set value for the selector 3 to select the second clock line 12 is stored.

Reference numeral 4 denotes timing control for serially transmitting and receiving data between the communication control circuit 100 and the master device 9 via the data line 13 in synchronization with the first clock SCK1 or the second clock SCK2. This is a communication control timing generation circuit (control means). The communication control timing generation circuit 4 includes a control register (not shown) therein, and stores control data for controlling various control signals required for communication.

5 is a data shift register for storing 8-bit data, 6 is an address control circuit, 7 is an internal address bus, 8 is an internal data bus, 10 is a memory such as a RAM, and 11 is a first clock from the master device 9. SCK1
Is supplied to the communication control circuit 100 from the master device 9.
2 is a second clock line for supplying 2 to the communication control circuit 100, and 13 is a data line for serially transmitting and receiving data SDATA.

Communication control circuit 100 according to the first embodiment
Is composed of a pulse edge detection circuit 1, a switching register 2, a selector 3, a communication control timing generation circuit 4, a data shift register 5, an address control circuit 6, an internal address bus 7, an internal data bus 8, and a memory 10. .

Next, the operation will be described. FIG. 2 is a timing chart showing a clock switching operation of communication control circuit 100 according to the first embodiment shown in FIG.
In the following description, the clocks to be switched are the first clock SCK1 and the second clock SCK2, and the data transmitted and received between the communication control circuit 100 and the master device 9 is 8-bit serial data. However, the present invention is not limited to this, and the clock to be switched may be a plurality of clocks respectively supplied through a plurality of clock lines. May be transmitted and received.

First, in the initial state, the communication control circuit 10 is transmitted from the master device 9 via the second clock line 12.
To 0, the pulse of the second clock SCK2 is continuously supplied. Also, the first clock S fixed at the H level
CK1 is supplied to the communication control circuit 100 via the first clock line 11 (timings T21 to T2).
2).

Next, the address control circuit 6 selects the data shift register 5 in accordance with the address obtained via the internal address bus 7, and thereby the 8-bit data shift register 5 stored in the memory 10 such as a RAM. Data SDATA
Are read out using the direct memory access function and stored in the data shift register 5. As shown in the timing chart of FIG. 2, the data SDATA has the MSB of DA7 and the LSB of DA0. Then, the communication control timing generation circuit 4 synchronizes the data in the data shift register 5 via the data line 13 with the master in synchronization with the rising edge of the pulse of the second clock SCK2 supplied via the second clock line 12. Serially transmitted to the device 9 (timing T21 to T2
2).

Next, when switching the clock from the second clock SCK2 to the first clock SCK1, the master device 9 changes the first clock SCK1 from H level to L level.
The level is switched (timing T23). This allows
The pulse edge detection circuit 1 detects the H level of the first clock SCK1.
A falling edge from the level to the L level is detected (timing T23), a one-shot pulse P is generated, and output to the switching register 2 and the communication control timing generation circuit 4 simultaneously.

Next, when the one-shot pulse P output from the pulse edge detection circuit 1 is input, the set value in the switching register 2 is rewritten from the L level value to the H level value. Is switched to the first
The clock line 11 and the communication control timing generation circuit 4 are connected. In addition, since the one-shot pulse P is also output to the communication control timing generation circuit 4 at the same time, the communication control timing generation circuit 4 outputs the second clock SCK2
Stops control of data transmission and reception synchronized with.

The generation of the one-shot pulse P causes the communication control timing generation circuit 4 to use a direct memory access function from a memory 10 such as a RAM in order to execute data transmission and reception in synchronization with the pulse of the first clock SCK1. Then, the data SDATA for transmission / reception is read and stored in the data shift register 5.

The data SDATA stored in the data shift register 5 is transmitted via the data line 13 to the master device 6 in synchronization with the rising edge of the pulse of the first clock SCK1 continuously output from the master device 9. Is transmitted serially (at timings T24 to T2).
5). In the timing chart shown in FIG. 2, the data SD transmitted from the communication control circuit 100 to the master device 9
ATA (DB7, DB6, ..., DB0) is the MSB
The case of the first is shown.

The pulse edge detection circuit 1 does not generate the one-shot pulse P even if the pulse of the first clock SCK1 shown at the timing T24 to T25 is input, and detects a level change that has continued for a predetermined time. A one-shot pulse P is generated. Further, for example, when the level of the first clock SCK1 changes from the L level to the H level, a one-shot pulse P may be generated.

As described above, according to the first embodiment, the first clock SC detected by the pulse edge detection circuit
A one-shot pulse P is generated based on the falling edge of K1, a set value of the switching register is rewritten based on the generated one-shot pulse P, and a selector is set based on the set value in the switching register. First clock line and second clock line
The communication control timing generation circuit controls the data transmission to and from the master device in synchronization with a clock pulse sequentially selected via the selected clock line. Therefore, an interrupt request signal is generated, the clock is automatically switched in the communication control circuit without the intervention of the CPU operating based on the interrupt request signal, and data transmission / reception is performed in synchronization with the switched clock pulse. There is an effect that execution can be performed efficiently.

Embodiment 2 FIG. 3 is a block diagram showing a communication control circuit according to a second embodiment of the present invention. In the figure, reference numeral 1 denotes a signal level change of the first clock SCK1 on the first clock line 11, and A pulse edge detection circuit that outputs a one-shot pulse,
4 counts the pulses of the second clock SCK2, outputs a control signal when the counted number reaches a predetermined value, and
When a one-shot pulse is output from the pulse edge detection circuit 1, a counter (counting means) whose count number is set to an initial value, generates and outputs an overflow signal ov when a control signal output from the counter 14 is input. Overflow generating circuit (counting means).

Reference numeral 21 denotes a switching register (connection means) for returning the current set value to an initial value when the overflow signal ov output from the overflow generating circuit 15 is input.
Reference numeral 3 denotes a selector (connection means) for selecting and connecting one of the first clock line 11 and the second clock line 12 according to the set value set in the switching register 21.
It is. In the initial state, the switching register 21 contains
A set value for the selector 3 to select the second clock line 12 is set as an initial value. Reference numeral 41 denotes the master device 9 and the communication control circuit 2 via the data line 13.
A communication control timing generation circuit (control means) for performing timing control for serially transmitting and receiving data to and from 00.

5 is a data shift register for storing 8-bit data, 6 is an address control circuit, 7 is an internal address bus, 8 is an internal data bus, 10 is a memory such as a RAM, and 11 is a first clock from the master device 9. SCK1
Is supplied to the communication control circuit 200 from the master device 9 and the second clock SCK
2 is a second clock line for supplying 2 to the communication control circuit 200, and 13 is a data line used for serially transmitting and receiving data SDATA.

The communication control circuit 200 according to the second embodiment shown in FIG.
4, an overflow generating circuit 15, a selector 3, a switching register 21, a communication control timing generating circuit 41, a data shift register 5, an address control circuit 6, an internal address bus 7, an internal data bus 8, and a memory 10.

Next, the operation will be described. FIG. 4 is a timing chart showing a clock switching operation of communication control circuit 200 according to the second embodiment shown in FIG.
In the following description, two clocks to be switched are the first clock SCK1 and the second clock SCK2, and the data transmitted and received between the communication control circuit 200 and the master device 9 has an 8-bit length. is there.

First, in the initial state, the switching register 21
Since the L level value is set as an initial value in, the selector 3 connects the second clock line 12 and the communication control timing generation circuit 41. Therefore, the pulse of the second clock SCK2 is continuously supplied from the master device 9 to the communication control timing generation circuit 41 via the second clock line 12. Also, H
The first clock SCK1 fixed at the level is supplied to the pulse edge detection circuit 1 via the first clock line 11.

Next, the address control circuit 6 selects the data shift register 5 based on the address obtained via the internal address bus 7. Then, the communication control timing generation circuit 41 reads 8-bit data SDATA to be transmitted using the direct memory access function from the memory 10 and stores the data SDATA in the data shift register 5. 8-bit data SD read from the memory 10
As shown in the timing chart of FIG.
SB is DA7 and LSB is DA0. Then, the communication control timing generation circuit 41 outputs the second clock SCK.
Data line 1 is synchronized with the rising of pulse 2
The data SDATA in the data shift register 5 is serially transmitted to the master device 9 via the data transfer register 3.

Next, when switching the clock from the second clock SCK2 to the first clock SCK1, the master device 9 switches the level of the first clock SCK1 from H level to L level. Thereby, the pulse edge detection circuit 1 detects the falling edge of the first clock SCK1 (timing T41), and the one-shot pulse P
And outputs it to the counter 14, the switching register 21, and the communication control timing generation circuit 41 at the same time.

Upon receiving the one-shot pulse P output from the pulse edge detection circuit 1, the switching register 21 rewrites the set value in the switching register 21, as in the case of the communication control circuit 100 of the first embodiment. A control signal is output to the selector 3. Upon input of the control signal, the selector 3 automatically switches the connection from the second clock line 12 to the first clock line 11. Thereby, the first clock line 11 and the communication control timing generation circuit 4
1 is connected to the master device 9 and the serial data SDA synchronized with the pulse of the first clock SCK1.
It becomes a state in which transmission and reception of TAs can be performed.

The transmission / reception operation of the serial data SDATA synchronized with the pulse of the first clock SCK1 is the same as that of the first embodiment, and the description is omitted here.
Therefore, in the communication control circuit 200, the second clock SCK
The operation of automatically switching from the second clock to the first clock SCK1 and transmitting data can be executed between timings T41 and T42 in the timing chart shown in FIG. 4, but in the description of the second embodiment, the second After switching from the clock SCK2 to the first clock SCK1, the first clock SCK1
To explain the operation of automatically switching to the second clock SCK2 when the pulse of CK1 is not input for a predetermined time,
Between the timings T41 to T42 shown in FIG. 4, the pulse of the first clock SCK1 or the data SD to be serially transmitted is transmitted.
The ATA is not shown.

The first clock SCK1 is supplied to the counter 14.
Edge detection circuit 1 with falling edge of
Since the one-shot pulse P generated and output in is input, the count number is automatically set to the initial value (timing T41). Then, between the timing T41 of the timing T42, in synchronization with a rising edge of a pulse of the second clock SCK2 counts the second clock _{SCK2 (MM 16, MM 16-1,} MM 16-2, ...., 0
2 ₁₆ , 01 ₁₆ , 00 ₁₆ ). As shown in the timing chart of FIG. 4, after the timing T41, since the one-shot pulse P is not output from the pulse edge detection circuit 1 to the counter 14, the count number is not initialized. Therefore, the count reaches a predetermined value (at timing T4).
2) The counter 14 generates a control signal and outputs it to the overflow generation circuit 15. The overflow generation circuit 15
When a control signal from the counter 14 is input, an overflow signal ov is generated and output to the switching register 21.

The switching register 21 returns the set value to the initial value when the overflow signal ov is input. That is, when the overflow signal ov is input, the switching register 21
Is set from the H level value to the L level value, whereby the selector 3 selects and switches the second clock line 12, and the master device 9 transmits the second clock line 12 via the second clock line 12. The clock SCK2 is supplied to the communication control timing generation circuit 41. Then, the communication control timing generation circuit 41 enters a state in which data transmission / reception based on the second clock SCK2 can be executed.

The communication control timing generation circuit 41
Reads data SDATA to be transmitted from a memory 10 such as a RAM using a direct memory access function, and stores the data SDATA in the data shift register 5. Then, the data SD stored in the data shift register 5
The ATA is serially transmitted to the master device 9 via the data line 13 in synchronization with the rising edge of the pulse of the second clock SCK2 continuously supplied from the master device 9 (timings T43 to T44).
In the timing chart shown in FIG. 4, the master device 9 is transmitted from the communication control circuit 200 via the data line 13.
Serial data SDATA (DB7, DB
6 ,. . . , DB0) show an example in the case of MSB first.

FIG. 5 shows the communication control circuit 200 shown in FIG.
FIG. 21 is a block diagram showing another configuration of the present invention.
Inputs a plurality of clocks, for example, an n-th clock SC
The pulse edge detection circuit detects a level change of a falling edge of a clock other than Kn and stores a value corresponding to the detected clock in a register. A decoder 54 decodes a value stored in a register in the pulse edge detection circuit 51 and outputs a decoding result. A decoder 52 stores a set value for selecting and switching a clock line in accordance with the decoding result output from the decoder 54. A switching register (connection means) 53 for selecting one of a plurality of clock lines according to the set value set in the switching register 52 and switching the connection (connection means), and 59 is a master device.

The other components of the communication control circuit 300 shown in FIG. 5 are the same as those of the communication control circuit 200 shown in FIG. 3, so that the description thereof is omitted here. Also,
In the communication control circuit 300 shown in FIG. 5, the n-th clock SCKn input via the n-th clock line is the second clock SCK in the communication control circuit 200 shown in FIG.
CK2, and the other clock SCK (n
-1),. . . , SCK1, unlike the master device 5
9 is a clock in which pulses are always continuously supplied to the counter 14 in the communication control circuit 300.

The switching register 5
The decoding result output to 2 is also output to the counter 14 at the same time. Thereby, the pulse edge detection circuit 51
Detects a change in the level of a clock other than the n-th clock SCKn, the count number is initialized and returned to the initial value, as in the case of the communication control circuit 200 shown in FIG.
Similarly to the case of the communication control circuit 200 shown in FIG. 3, when there is no change in the level of a clock other than the n-th clock SCKn for a predetermined time, the count number obtained by counting the pulses of the n-th clock SCKn is equal to a predetermined number. When the number is reached, a control signal is output from the counter 14 to the overflow generation circuit 15.

The overflow generating circuit 15 receives a control signal from the counter 14 and outputs an overflow signal o.
v, and the generated overflow signal ov is output to the switching register 52, and the set value of the switching register 52 is set to the initial value. Thereby, the selector 53
Automatically switches the connection to the nth clock line, so that the communication control timing generation circuit 41 synchronizes with the master device 59 in synchronization with the pulse of the nth clock SCKn supplied via the nth clock line. It becomes possible to control the transmission and reception of the data. The operation of this data transmission / reception is the same as that of the communication control circuit 100 shown in FIG. 1 or the communication control circuit 200 shown in FIG.

As described above, according to the second embodiment, the first clock SC detected by the pulse edge detection circuit
When the one-shot pulse P is generated based on the falling edge of K1, the counter initializes the count value, and the count reaches a predetermined value without the input of the one-shot pulse P, that is, the first clock When the SCK1 is in the unused state for a predetermined time, the overflow generation circuit generates an overflow signal ov and outputs it to the switching register. Is automatically connected to the second clock line, so that the clock is automatically selected and switched in the communication control circuit without the intervention of the CPU operating based on the interrupt request signal, and the clock is synchronized with the switched clock. Thus, there is an effect that data can be transmitted and received efficiently. Also, when switching clocks obtained through three or more clock lines, a value indicating the state of each clock line is stored in a register in the pulse edge detection circuit, and this is decoded by a decoder, and the decoding result is obtained. Since the setting value is set in the switching register based on the above, the clock can be automatically selected and switched in the communication control circuit without the intervention of the CPU.

[0049]

As described above, according to the present invention, one shot pulse is generated based on the falling edge of the clock detected by the pulse edge detection circuit, and the one shot pulse is generated based on the generated one shot pulse. The setting value of the switching register as the connecting means is rewritten, and the selector as the connecting means selects the clock line based on the setting value in the switching register, and synchronizes with the clock pulse supplied through the selected clock line. Since the communication control timing generation circuit as control means is configured to transmit and receive data to and from a master device as an external device, it is necessary to generate an interrupt request signal and transmit it to the CPU when switching clocks. No clock is automatically switched within the communication control circuit without the intervention of a CPU that operates based on the generation of an interrupt request signal In synchronization with the switching clock pulses, there is an effect that it is possible to perform efficiently the data transmission and reception between the external device.

According to the present invention, a one-shot pulse is generated based on the falling edge of the clock detected by the pulse edge detection circuit, and the counter as counting means counts based on the generated one-shot pulse. When the count value reaches a predetermined value without input of a one-shot pulse, that is, when the clock is in an unused state for a predetermined period, an overflow generation circuit as a counting means generates an overflow signal. Output to a switching register as switching means, and when the switching register inputs an overflow signal, the selector as connecting means is configured to automatically connect a predetermined clock line, so that it operates based on an interrupt request signal. CPU
In this case, the clock can be automatically selected and switched in the communication control circuit without any intervention, and data can be transmitted and received efficiently in synchronization with the switched clock. Even when switching clocks obtained through a plurality of clock lines, a detection value indicating the state of each clock line is stored in a register in the pulse edge detection circuit, and this is decoded by a decoder, and based on the decoding result. Since the setting value is set in the switching register and the selector selects and switches the clock line based on the setting value, the clock is automatically selected in the communication control circuit without the intervention of the CPU. Can be switched.

[Brief description of the drawings]

FIG. 1 is a block diagram showing a communication control circuit according to a first embodiment of the present invention.

FIG. 2 is a timing chart showing a clock switching operation of the communication control circuit shown in FIG.

FIG. 3 is a block diagram showing a communication control circuit according to a second embodiment of the present invention.

FIG. 4 is a timing chart showing a clock switching operation of the communication control circuit shown in FIG. 3;

FIG. 5 is a block diagram showing another configuration of the communication control circuit shown in FIG. 3;

FIG. 6 is a block diagram showing a conventional communication control circuit.

7 is a timing chart showing a clock switching operation of the conventional communication control circuit shown in FIG.

[Explanation of symbols]

1,51 pulse edge detection circuit, 2,21,52 switching register (connection means), 3,53 selector (connection means), 4,41 communication control timing generation circuit, 5
Data shift register, 6 address control circuit, 7 internal address bus, 8 internal data bus, 9, 59 master device, 10 memory, 11 first clock line, 12 second clock line, 13 data line,
14 counter (counting means), 15 overflow generating circuit (counting means), 54 decoder, 100, 2
00,300 Communication control circuit.

 ──────────────────────────────────────────────────続 き Continued on the front page F term (reference) 5B077 FF11 GG05 GG32 MM02 5K047 AA02 GG03 GG24 MM12 MM56

Claims (3)

[Claims] 1. A circuit connected to a plurality of clock lines for supplying a plurality of clocks other than an n-th clock line for supplying an n-th clock, detecting levels of the plurality of clocks, and corresponding to a clock having a level change. A pulse edge detection circuit that generates and outputs a one-shot pulse, and is connected to the n-th clock line in an initial state;
Connection means for switching connection to the clock line corresponding to the clock having the level change when the one-shot pulse is input, and controlling transmission / reception of data in synchronization with the pulse of the n-th clock in an initial state; A communication control circuit for controlling data transmission and reception in synchronization with the clock pulse supplied via the clock line connected by the connection means when the one-shot pulse is input; . 2. An n-th clock pulse, which is always supplied via an n-th clock line, is counted. When the count reaches a predetermined value, an overflow signal is generated and output, and the overflow signal is output from the pulse edge detection circuit. The apparatus further includes a count unit that sets the count number to an initial value when a one-shot pulse is input, and the connection unit outputs the count value output from the count unit in a state where a clock line other than the n-th clock line is connected. 2. The communication control circuit according to claim 1, wherein when an overflow signal is input, connection is switched to said n-th clock line, and said n-th clock is supplied to said control means. 3. The pulse edge detection circuit includes a register, further includes a decoder that stores a value corresponding to a level change of a plurality of clocks other than the n-th clock, and decodes the value stored in the register. 3. The communication control circuit according to claim 1, wherein the means switches connection of the clock line according to a decoding result output from the decoder.