JPS6336052U - - Google Patents

Info

Publication number
JPS6336052U
JPS6336052U JP1986129468U JP12946886U JPS6336052U JP S6336052 U JPS6336052 U JP S6336052U JP 1986129468 U JP1986129468 U JP 1986129468U JP 12946886 U JP12946886 U JP 12946886U JP S6336052 U JPS6336052 U JP S6336052U
Authority
JP
Japan
Prior art keywords
motherboard
top surface
logic lsi
chip module
heat dissipation
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
JP1986129468U
Other languages
Japanese (ja)
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed filed Critical
Priority to JP1986129468U priority Critical patent/JPS6336052U/ja
Publication of JPS6336052U publication Critical patent/JPS6336052U/ja
Pending legal-status Critical Current

Links

Classifications

    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/26—Layer connectors, e.g. plate connectors, solder or adhesive layers; Manufacturing methods related thereto
    • H01L2224/31—Structure, shape, material or disposition of the layer connectors after the connecting process
    • H01L2224/32—Structure, shape, material or disposition of the layer connectors after the connecting process of an individual layer connector
    • H01L2224/321—Disposition
    • H01L2224/32151—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
    • H01L2224/32221—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
    • H01L2224/32225—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42—Wire connectors; Manufacturing methods related thereto
    • H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
    • H01L2224/481—Disposition
    • H01L2224/48151—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
    • H01L2224/48221—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
    • H01L2224/48225—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation
    • H01L2224/48227—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation connecting the wire to a bond pad of the item
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/73—Means for bonding being of different types provided for in two or more of groups H01L2224/10, H01L2224/18, H01L2224/26, H01L2224/34, H01L2224/42, H01L2224/50, H01L2224/63, H01L2224/71
    • H01L2224/732—Location after the connecting process
    • H01L2224/73251—Location after the connecting process on different surfaces
    • H01L2224/73265—Layer and wire connectors
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
    • H01L24/73—Means for bonding being of different types provided for in two or more of groups H01L24/10, H01L24/18, H01L24/26, H01L24/34, H01L24/42, H01L24/50, H01L24/63, H01L24/71

Description

【図面の簡単な説明】[Brief explanation of the drawing]

第１図は、本考案の実施例の断面図、第２図は
他の実施例の断面図、第３図はさらに他の実施例
の断面図、第４図は従来のマルチチツプモジユー
ルの構成図、第５図、第６図は、本考案の別の実
施例の説明図である。 １……放熱フイン、２……ＲＡＭ、３……チツ
プキヤリア、４……スペーサ、５……セラミツク
基板、６……リードフレーム、７……キヤツプ、
８……論理ＬＳＩ、９……リード。 FIG. 1 is a sectional view of an embodiment of the present invention, FIG. 2 is a sectional view of another embodiment, FIG. 3 is a sectional view of still another embodiment, and FIG. 4 is a sectional view of a conventional multichip module. The configuration diagram, FIG. 5, and FIG. 6 are explanatory diagrams of another embodiment of the present invention. 1... Heat dissipation fin, 2... RAM, 3... Chip carrier, 4... Spacer, 5... Ceramic substrate, 6... Lead frame, 7... Cap,
8...Logic LSI, 9...Read.

Claims (1)

【実用新案登録請求の範囲】[Scope of utility model registration request] セラミツク基板より成るマザーボード下面に論
理ＬＳＩを配置し、上述マザーボード上面に複数
のチツプキヤリア式のＲＡＭを配置したマルチチ
ツプモジユールにおいて、マザーボード上面のＲ
ＡＭおよび論理ＬＳＩ配置位置の裏側であるマザ
ーボード上面に直接接触するように、一体ででき
た。放熱フインを設けたことを特徴とするマルチ
チツプモジユール。 In a multi-chip module in which a logic LSI is placed on the bottom surface of a motherboard made of a ceramic substrate and a plurality of chip carrier type RAMs are placed on the top surface of the motherboard, the R on the top surface of the motherboard is
It was made in one piece so that it directly contacts the top surface of the motherboard, which is the back side of the AM and logic LSI placement locations. A multi-chip module characterized by the provision of heat dissipation fins.
JP1986129468U 1986-08-27 1986-08-27 Pending JPS6336052U (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP1986129468U JPS6336052U (en) 1986-08-27 1986-08-27

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP1986129468U JPS6336052U (en) 1986-08-27 1986-08-27

Publications (1)

Publication Number Publication Date
JPS6336052U true JPS6336052U (en) 1988-03-08

Family

ID=31026062

Family Applications (1)

Application Number Title Priority Date Filing Date
JP1986129468U Pending JPS6336052U (en) 1986-08-27 1986-08-27

Country Status (1)

Country Link
JP (1) JPS6336052U (en)

Cited By (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPH0373458U (en) * 1989-11-22 1991-07-24
JPH0613540A (en) * 1991-12-03 1994-01-21 Nec Corp Multichip module
WO2008108335A1 (en) * 2007-03-06 2008-09-12 Nikon Corporation Semiconductor device

Cited By (4)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPH0373458U (en) * 1989-11-22 1991-07-24
JPH0613540A (en) * 1991-12-03 1994-01-21 Nec Corp Multichip module
WO2008108335A1 (en) * 2007-03-06 2008-09-12 Nikon Corporation Semiconductor device
JP5521546B2 (en) * 2007-03-06 2014-06-18 株式会社ニコン Semiconductor device

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