JPS63318670A - Processor for processing digital signal - Google Patents

Abstract

PURPOSE:To execute one instruction/one cycle time of a multiplication shifting operation, shift data, other data memory, an arithmetic logical operation, etc., by preparing two shifters whose shape are incidental to a multiplying circuit and an accumulator. CONSTITUTION:At the time of arithmetic logical operation, here, as one example, one side data to execute the arithmetic logical operation is stored into an accumulator 27, the shift value is prepared for a shifter 29 and other side data are read from a second data RAM 7. At a first step, the reading address of the second data RAM 7 is loaded to a data RAM address counter 6. At a second step, the address contents of the RAM 7 and the data converted to the shift data by the shifter 29 from the accumulator 27 and to pass through an accumulator output selector 30 are inputted to an ALU 25, and the arithmetic logical operation is executed. At a third step, they are latched to accumulators 27 and 28, and the shift setting value of the shifter 29 is set.

Description

DETAILED DESCRIPTION OF THE INVENTION (Field of Industrial Application) The present invention relates to the configuration of a digital signal processing processor that processes digital signals at high speed.

(Prior Art) Conventional processors for digital signal processing include, for example, Japanese Patent Laid-Open No. 101266/1983, Nippon Electric Technical Report No.
l:15/1980, NEC Corporation, p44-
There is one disclosed in No. 46. FIG. 2 is a block diagram showing an example of the configuration of a conventional signal processing processor of this type. This signal processing processor includes a sequence control section, a data RAM section, a data ROM section, a multiplier (hereinafter abbreviated as MPY) section, an arithmetic logic unit (hereinafter abbreviated as ALU) section, and an input/output interface section. and a main bus 500 that connects these functional blocks.

The sequence control section includes a program memory 170 that stores programs for signal processing, and a program memory 170 that stores programs for signal processing.
70, and a stack 172 that outputs jump instructions and the like to the program counter 171. The data RAM section is a one-sided data RA that stores temporary data during calculations in real-time processing and variable data such as coefficients of variable characteristic filters.
M150 and data RA under control by the program.
Data RA that controls memory read etc. of M150
It consists of an M address counter 151. The data ROM section stores digital filter coefficients and p in nonlinear PCM.
It consists of a data ROM 152 that stores fixed data such as a -Law/A-Law code conversion table, and a data ROM address counter 153 that controls reading of the data ROM 152. MPY section is selection circuit 1
55, 156 and M PY 160 which performs the multiplication. The Al1 section is the ALU 161 that executes calculations.
, an accumulator 162 for accumulating the operation result of the ALU 161, 16:1, and a carry register 16.
4,165, a selection circuit 166 that selects one of the accumulator outputs, a shifter 167 that shifts and controls the signal from the selection circuit 166, an MPY output bus 168, and a selection circuit 169. The input/output interface, the ace part, has a serial input register 173 and a serial output register 17.
4, output port 175, and parallel input/output register 1
76, a control register 177, an output port 178,
It consists of a serial input/output clock terminal 180, a serial input terminal t8t, and a serial output terminal 182.

As described above, the conventional signal processing processor has two accumulators 162 and 163 and a shifter 167 attached to the Al1 section, and has a configuration advantageous for product-sum calculation processing such as filtering calculation.

(Problems to be Solved by the Invention) However, in the signal processing processor with the above configuration,
When performing a digit shift operation on the multiplication result, a shift instruction is specified following the multiplication instruction, and the data on the MPY output bus 168 is transferred to A.
The digit is shifted by passing through the ALU unit once again via L U 161, accumulators 162 and 163, and shifter 16.7.

Furthermore, when performing arithmetic and logical operations with other data memory output or MPY output data using the shifted data, the shifted data is once stacked in the accumulators 162 and 163 via the ALU section. The format is to perform calculations from.

This not only complicates the processing process but also increases the calculation time.

The present invention eliminates problems such as complicating the processing process and increasing calculation time when executing the multiplication instructions and shift instructions described above and performing operations using shift data, thereby achieving superior high-speed processing. The purpose of this invention is to provide a processor for digital signal processing.

(Means for Solving the Problems) In order to solve the problems of the prior art, the digital signal processing processor of the present invention includes a program memory for storing programs, and a control circuit for controlling reading of the program memory. , a three-sided data memory for storing two-variable data and read-only memory control data, and an address pointer provided corresponding to each data memory and setting a memory read address under control by the program; a read-only memory that is provided independently of the data memory, stores fixed data, sets a read address and reads contents by the program and the data memory; and a multiplier that takes in a multiplier and a multiplicand input and executes multiplication. a first shifter that shifts and controls the multiplication result of the multiplication circuit; an arithmetic logic circuit that takes in two inputs and performs an arithmetic and logic operation; and a calculation result of the arithmetic and logic circuit that is stored in one or both of them. a second shifter for shifting and controlling the contents of the accumulators; means for selecting one of the accumulator outputs; a serial input register, a serial output register, a parallel input register, and a parallel output register; an input/output interface section held by the controller; a data bus commonly connected to each block of the control circuit, data memory, read-only memory, multiplication circuit, arithmetic logic circuit, and input/output interface section; and a stage preceding the data memory. and a temporary storage register for temporarily storing the contents of the data bus.

(Operation) In the present invention, for example, during multiplication, each technical means operates as follows. The control circuit reads a multiplication execution program from the program memory and controls each section via the data bus. The multiplication circuit receives a multiplier and a multiplicand and executes multiplication, and the three-sided data memory, read-only memory, and accumulator supply their outputs to the multiplication circuit as a multiplier or multiplicand. ``The three-sided data memory can use two sides for variable data and the remaining one side for storing readout control data of the read-only memory. The multiplication circuit executes multiplication using the input multiplier and multiplicand, the first shifter performs a shift operation on the multiplication result, and the result is latched.

Furthermore, in the case of arithmetic and logical operations, the control circuit reads out the program for the arithmetic and logical operations, and each section is program-controlled via the data bus. The two inputs of the arithmetic and logic circuit are a data memory, a read-only memory, an accumulator, and the output of the main bus. For example, one input is an accumulator output, and the other input is data in one of the three-sided data memories. One data is stored in an accumulator and is shifted and controlled by a second shifter. This shifted data is supplied to one input of the arithmetic and logic circuit. The other data is output from the data memory whose reading is controlled by the corresponding address pointer, and is supplied to the other input of the arithmetic and logic circuit. The arithmetic logic operation circuit is 2
Perform arithmetic and logical operations based on input. Then, the result of the operation is latched in one or both of the accumulators.
The shift value of the second shifter is set.

In this way, by shift control using the first and second chics provided along with the multiplier circuit and the accumulator,
Multiplication, shift operations, and arithmetic and logic operations are possible with one instruction and one cycle time. Furthermore, a three-sided data memory, a temporary storage register for storing data on the data bus, and registers provided independently for parallel/serial and input/output work to improve parallel processing capability. Therefore, faster arithmetic processing is possible, and the problems of the prior art described above are solved.

(Example) Examples of the present invention will be described in detail below.

FIG. 1 is a block diagram showing the configuration of a digital signal processing processor of this embodiment. This signal processing processor includes a sequence control section, a data RAM section, a data ROM section, an MPY section, an ALU section, an input/output interface section, a data bus 31 common to each section, and a large number of auxiliary data buses. It is composed of □. The sequence section includes a stack 1 that outputs jump instructions, etc., and a program counter (PC) that controls reading of the program memory 3.
) 2. Program memory 3 for storing signal processing programs and pipeline register 4 for matching processing instructions.
Consists of. The data RAM section is a three-sided data RAM, that is, a first data RAM 8 and a second data RAM. and a third data RAM 10, and first to third data RAMs that respectively set the memory read addresses of these data RAMs 8, 7.10 under the control of the notation program.
Address counter (MPO)5. (MPI) 6, (MPI)
2) 9, data RAM selector 14, and data RAM
An input selector 15 and first and second temporary storage registers (for temporarily saving the contents on the main bus 31).
TRI) 16° (TR2) 17°. data ROM
The section is provided independently of the data RAM 8, 7.10, stores fixed data, and stores the program and third data R.
A data ROM 13 whose read address is set and whose contents are read by AM10, and a data ROM address counter (RP) 12 which controls reading of the data ROM 13.
and a data ROM address selector 11. MP
The Y section includes a latch input selector 18 for selecting and inputting a multiplier for multiplication, a latch input selector 20 for selecting and inputting a multiplicand, an MPY driver latch (19) for latching the multiplicand, and an MPY driver latch (19) for latching the multiplicand. 21, an MPY 22 that performs multiplication using the input multiplier and multiplicand, a shifter (MSFT) 23 that shifts the multiplication result of MPY 22, and an MPY output latch (ML) 24 that latches the shift result. The ALU section includes an ALU 25 that receives two inputs from the data RAM output, data ROM output, MPY output, accumulator contents, and main bus contents and performs calculations, and a flag register for detecting overflow of the calculation result by monitoring flags of the ALU 25. (FLAG REG) 26 and ALU2
first and second accumulators (ACCO) 27. (ACCI
) 2B, a shifter (ASFT) 29 that shifts the contents of the first accumulator (ACCI) 27, and a first accumulator (ACCO) 27 or shifter (ASFT)
The accumulator output selector 30 selects one of the contents of 29 and inputs it to the ALU 25. The input/output interface section includes a serial output register (Sol) 34° (302) 32 and a serial input register (sil) 35, which are provided independently. (SI2) 33, parallel output register (OR) 40, parallel input register (
IR) 41, serial output terminals 36, 38, serial input terminals 37, 39, and parallel input/output ports 42.

Immediate data from the program memory 3 and input data from the input/output interface section are transferred to the main bus 3.
1 is input. The data RAM 8.7.10 has a three-sided structure, each having its own address counters 5 and 6.9. In this embodiment, the first and second data RA
M8.7 stores two variable data, and the third data RAM
l0 stores data ROM read control data.

The output of the first data RAM 8 passes through the data RAM output selector 14 to the latch input selector 18 and A of the MPY section.
It is input to the P side of the LU 25 and the main bus 31. Second
In addition to the route input to the main bus 31, the output of the data RAM 7 passes through the data RAM output selector 14 to the M
The PY section has a route that is input to the latch input selector 18 and the P side of the ALU 25, and a route that is input to the L latch input selector 20 of the MPY section and the Q side of the ALU 25. The output of the third data RAM 10 is input to the data ROM address selector 11 and the main bus 31. The data ROM 13 has a one-sided configuration and has its own address counter (RP) 12 and address selector 11.

The input to the address selector 11 is the third data RAM1.
There are two routes: 0 output route and main bus 31 route. The output of the data ROM 13 is input to the main bus 31, the latch input selector 20 of the MPY section, and the Q side of the ALU 25. The input to the Q side of the ALU 25 is the main bus 31.
It also has a route. The output of the ALU 25 is sent to the first and second accumulators (ACCo) 27. (ACC)28
input to either or both. The output of the first accumulator (ACCO) 27 is the shifter (ASFT) 2
9 and is input to the main bus 31 and the accumulator output selector 30. Second accumulator (ACC
The output of I) 28 is input to the main bus 31 and the accumulator output selector 30. The data selected by the accumulator output selector 30 is input to the latch input selector 18 of the MPY section and the P side of the ALU 25.

Further, from the main bus 31, output registers (Sol) 34. of the input/output interface section are connected. (S02)32. (OR
) 40, each data RAM address counter 5, 6°9,
Data RAM input selector 15, first and second time storage registers (TRI) 16. (TR2) Input to 17 is also possible.

As described above, in this embodiment, there is a main bus 3 between each element.
Many auxiliary buses other than 1 are connected.

Next, the operation of this embodiment will be explained in terms of multiplication and arithmetic and logic operations.

First, let's talk about multiplication. Here, it is assumed that the multiplier and multiplicand for multiplication are read from the first and second data RAMs 8.7. In the first step, the read addresses of the first and second data RAMs 8.7 are loaded into the RAM address counter 5.6. In the second stage, the contents of each address of the first and second data RAMs 8.7 are read out, and at the same time, the contents are outputted via the data RAM output selector 14, K latch input selector 18, and L latch input selector 20. , the multiplier and the multiplicand are latched in the latch 19 and the latch 21, and the MPY unit 2 and the shifter 23 execute a multiplication and shift operation. In the third stage, the MPY output latch 24 latches the result of the multiplication and shift operation.

In addition, in the above, the input of the multiplier and the multiplicand is from the first and second data RAM8.7, but for example, the input of the multiplier and the multiplicand is
The output of the data RAM 7 and the data ROM 13 may be latched as the multiplicand. In this case, the control data stored in the third data RAM10 causes the data RO
Reading of M13 is performed. Of course, other connections are also possible.

Next, we will discuss arithmetic and logical operations. Here, as an example, it is assumed that one data to be subjected to an arithmetic and logical operation is stored in the accumulator 27, its shift value is prepared in the shifter 29, and the other data is read out from the second data RAM 7.

In the first stage, the data RAM address counter 6 is loaded with the read address of the second data RAM 7. Second
At this stage, the address contents of the second data RAM 7 and the data converted from the accumulator 27 into shift data by the shifter 29 and passed through the accumulator output selector 30 are input to the ALU 25, and an arithmetic and logic operation is executed. It is latched into accumulators 27 and 28 in the third stage.

The shift setting value of shifter 29 is set.

In this case as well, it goes without saying that arithmetic and logical operations can be performed using other inputs than those mentioned above as the two inputs of the ALU 25.

(Effect of the invention) 1-. As explained in detail, according to the present invention, two shifters are provided which are attached to the multiplier circuit and the accumulator, so that the multiplier shift operation and shift data and other data memory, read-only memory, and multiplier circuit output are provided. , arithmetic and logical operations with data from the main bus can each be executed in one cycle time per instruction, and the effect of significantly reducing processing steps can be expected for division processing as well. Furthermore, three-sided data memory with independent address pointers and read-only memory are provided, a temporary storage register is provided to temporarily save data on the data bus, and the interface with the outside is By installing registers in γ (parallel/serial, output/input), it has excellent parallel processing ability and can be expected to achieve faster arithmetic processing effects.

[Brief explanation of the drawing]

FIG. 1 is a block diagram showing the configuration of a digital signal processing processor according to the present invention, and FIG. 2 is a block diagram showing the configuration of a conventional digital signal processing processor. 2.-Program counter 3.-Program memory 5.6.9--Data RAM address counter 7.8
．． 10--Data RAM 13-Data ROM 16.17--Temporary storage register 22--Multiplier (MPY) 23-Shifter 25--Arithmetic logic unit (ALU) 27.28--Accumulator 29--Shifter 31 −Main bus

Claims (1)

[Scope of Claims] A program memory that stores a program, a control circuit that controls reading of the program memory, and a three-sided data memory that stores two-variable data and read-only memory control data; an address pointer that is provided corresponding to each data memory and sets a memory read address under the control of the program; and an address pointer that is provided independently of the data memory and stores fixed data and sets a read address under the control of the program and the data memory. A read-only memory in which settings and contents are read; a multiplication circuit that takes in multiplier and multiplicand inputs and executes multiplication; a first shifter that shifts and controls the multiplication results of the multiplier circuit; and an arithmetic logic that takes in two inputs. an arithmetic logic operation circuit that performs an operation; two accumulators that accumulate the operation results of the arithmetic logic operation circuit in one or both; a second shifter that shifts and controls the contents of the accumulator; and one of the accumulators. means for selecting an output; an input/output interface unit independently holding a serial input register, a serial output register, a parallel input register, and a parallel output register; and the control circuit, data memory, read-only memory, multiplication circuit, and arithmetic logic. A data bus commonly connected to each block of an arithmetic circuit and an input/output interface section, and a temporary storage register provided at a stage before the data memory to temporarily store the contents of the data bus, The memory output, the read-only memory output, and the accumulator contents are used as the multiplier and multiplicand inputs of the multiplication circuit, and the data memory output, the read-only memory output, the multiplication circuit output, the accumulator contents, and the data bus contents are used as the two inputs of the arithmetic logic circuit. A digital signal processing processor characterized by: