JPS63318669A - Processor for processing digital signal - Google Patents

Abstract

PURPOSE:To attain the multiplication of two variable input arithmetic logical operation, execution of a shift control etc. without using exclusively a main bus in one instruction by providing many auxiliary buses used efficiently besides the main bus. CONSTITUTION:At the time of multiplying, the reading address of first and second data RAM 8 and 7 is loaded to RAM address counters 5 and 6 at a first step. At a second step, the contents of respective address of the RAM 8 and 7 are read and simultaneously, the contents are outputted through a data RAM output selector 14, a K latch input selector 18 and an L latch input selector 20. The contents are latched as a K latch 19 and an L latch 21 as a multiplier and a multiplicand and the multiplication shifting operation is executed by an MPY 22 and a shifter 23. At a third step, the multiplication shifting operation result is latched to an MPY output latch 24. For example, the second data RAM 7 may be latched as the multiplier and the output of data ROM 13 may be latched as the multiplicand.

Description

DETAILED DESCRIPTION OF THE INVENTION (Field of Industrial Application) The present invention relates to a digital signal processing processor, and particularly to a connection configuration between functional components of a digital signal processing processor.

(Prior Art) Conventional processors for digital signal processing include, for example, Japanese Patent Laid-Open No. 101266/1983, Nippon Electric Technical Report No.
l:15/1980, F1 Hondenki Co., Ltd., p4
There is one disclosed in No. 4-46. FIG. 2 is a block diagram showing an example of the configuration of a conventional signal processing processor of this type. This YES processing processor includes a sequence control section, a data RAM section, a data ROM section, a multiplier (hereinafter abbreviated as MPY) section, and an arithmetic logic unit (hereinafter referred to as AL).
The main bus 500 connects these functional blocks to each other. The sequence control unit includes a program memory 170 that stores programs for signal processing, and a program counter 1 that controls reading of the program memory 170.
71 and a stack 172 that outputs jump instructions and the like to the program counter 171. The data RAM section stores temporary data during calculations in real-time processing and n (variable data) such as coefficients of variable characteristic filters, and a data RAM 150 that stores data RAM 150 under the control of the program. Consists of a data RAM address counter 151 that controls memory reading, etc. Data R
The OM section includes a data ROM 152 that stores fixed data such as digital filter coefficients and μmLaw/A-Law code conversion tables in nonlinear PCM;
Data R that controls reading of the data ROM 152
It consists of an OM address counter 153. The MPY unit includes selection circuits 155 and 156, and MPY1 that executes multiplication.
Consists of 60. The ALU section executes calculations.
161, accumulators 162 and 163 that accumulate the operation results of the ALU 161, and a carry register 1.
64, 165, a selection circuit 166 that selects one of the accumulator outputs, a shifter 167 that shifts and controls the signal from the selection circuit 166, an MPY output bus +68, and a selection circuit 169. The input/output interface section includes a serial input register 173 and a serial output register 17.
4, output port 175, and parallel input/output register 1
76, control register +77, output port 178,
It consists of a serial input/output clock terminal 180, a serial input terminal 181, and a serial output terminal 182.

In the conventional signal processing processor described above, most of the functional blocks are connected to the main bus 500. However, since many instructions such as arithmetic processing require two source data, the reality is that several auxiliary buses are provided. For example, in the MPY section, between the selection circuit 155 and the output of the data RAM 150, and between the selection circuit 1
56 and the data ROM 152 are connected by an auxiliary bus, so that the multiplier and multiplicand can be input at the same time. Also, in the ALU section, the selection circuit 169 and the MP
The data RAM 160, the data RAM 150, and the shifter 167 are connected by an auxiliary bus, thereby reducing the occupancy of the main bus 500.

(Problems to be Solved by the Invention) However, in the signal processing processor with the above configuration,
When performing multiplication of two variables or arithmetic and logical operations, it cannot be performed using the - instruction, and when data stored in the data RAM is subjected to logarithmic conversion or trigonometric conversion using the data ROM, the main bus 500 is occupied. There was a point.

This invention eliminates the problem of not being able to perform the above-mentioned two-variable operation in one instruction and the high occupancy of the main bus.
It is an object of the present invention to provide a digital signal processing processor with excellent parallel processing performance.

(Means for Solving the Problems) In order to solve the problems of the prior art, the digital signal processing processor of the present invention includes a sequence control section that performs program control for signal processing, and a storage system for storing two-variable data. first and second data RAMs and data ROMs that perform
i (a third data RAM for storing non-J data;
Data R for selecting inputs of the first and second data RAMs
an AM input selector, a data RAM address counter that sets the memory read address of each data RAM, and a first
and a data RAM that selects the output of the second data RAM.
a data RAM section having an output selector and first and second temporary storage registers that are respectively provided before the first and second data RAMs and the third data RAM and temporarily store the contents of the main bus; , a data ROM which is provided independently of the +if data small data RAM, stores fixed data, and whose read address is set and whose contents are read under the control of the sequence control unit and the third data RAM; and the main bus. A data ROM that selects the output of the sequence control unit and the output of the third data RAM via the
a data ROM section having a selector and a data ROM address counter that controls reading of the data ROM;
a multiplier circuit section having a multiplication circuit that takes in multiplier and multiplicand inputs and executes multiplication; an arithmetic logic operation circuit that takes in two inputs and executes an arithmetic and logic operation; and an operation result of the arithmetic and logic operation circuit that is applied to either or both an arithmetic logic operation circuit unit having first and second accumulators for accumulating, a shifter for controlling the output of the first accumulator, and an accumulator output selector for selecting the output of the shifter and the second accumulator; It is equipped with an input/output interface section that has registers and output registers and exchanges signals with the outside, and a main bus that is a data bus that commonly connects the blocks of each section. A large number of auxiliary buses are provided to connect elements to each other, components in a block to components in another block, other blocks, and the main bus, and data RAM output, data ROM output, and accumulator contents are input to the multiplication circuit. The data RAM output, data ROM output, multiplication circuit output, accumulator contents, and main bus contents are input to the arithmetic and logic operation circuit.

The auxiliary bus includes, for example, an auxiliary bus from the first data RAM output to the data RAM output selector input and the main bus, and a second data RAM output to the data RAM output selector input and the main bus.
an auxiliary bus from the output selector input, the multiplication circuit section input, the arithmetic logic operation circuit section input and the main bus; an auxiliary bus from the data RAM output selector output to the multiplication circuit section input and the arithmetic logic operation circuit section input; An auxiliary bus from the data RAM output to the data ROM address selector input and main bus, an auxiliary bus from the data ROM address selector output to the data ROM address counter, and a data R
An auxiliary bus from the OM output to the multiplication circuit section input, an arithmetic logic operation circuit section input, and the main bus, an auxiliary bus from the multiplication circuit section output to the arithmetic logic operation circuit section input, and an auxiliary bus from the arithmetic logic operation circuit section output to the first and an auxiliary bus to a second accumulator input, an auxiliary bus from the first accumulator output to the shifter input, an auxiliary bus from the shifter output to the accumulator output selector input and the main bus, and an auxiliary bus from the second accumulator output to the accumulator output selector input. an auxiliary bus from the accumulator output selector output to the multiplier circuit input and the arithmetic logic circuit input; and an auxiliary bus from the first temporary storage register output to the data RAM input selector input. , an auxiliary bus from the second temporary storage register output to the third data RAM input, an auxiliary bus from the data RAM input selector output to the first and second data RAM inputs, and an auxiliary bus from the input register output to the main bus. A supplementary bus will be provided.

(Operation) In the present invention, for example, during multiplication, each technical means operates as follows. The sequence control section reads out a multiplication execution program and controls each section via the main bus. The multiplication circuit inputs the multiplier and the multiplicand and executes the multiplication, but the first and second data RAMs, data ROM, and first and second accumulators supply their outputs as the multiplier or the multiplicand to the multiplication circuit. do. First and second data RA
The output of M is selected by the data RAM output selector and supplied to the multiplication circuit. Data reading from the first and second data RAMs is performed by corresponding data RAM address counters. The variable data of the first and second data RAMs are input from the input/output interface section, and the data temporarily stored or not stored in the first temporary storage register is input to the data RAM via the main bus. It is selected by the selector and stored.

Data ROM stores fixed data, and reading it is
The read control output of the third data RAM is the data ROM.
The data is sent to the data ROM address counter via the selector, thereby controlling the data ROM address counter. . One of the first and second accumulator outputs is selected by an accumulator output selector and supplied to the multiplication circuit. When performing the following operations, in addition to the main bus, many auxiliary buses work so that each function can be operated separately with one command, so the main bus is not occupied during one command. , multiplication of two variable inputs by a multiplication circuit becomes possible.

Furthermore, in the case of arithmetic and logical operations, each technical means operates as follows. As the two inputs of the arithmetic and logic operation circuit, outputs or contents from the first and second data RAMs, data ROM, multiplication circuit, first and second accumulators, and main bus are used. For example, when the data in the first accumulator and the data in the second data RAM are two inputs, the data in the first accumulator is shifted by a shifter and input to one input of the arithmetic logic circuit via the accumulator output selector. Supplied. Second data RAM
The data is read out under the control of the corresponding data RAM address counter and supplied to the other input of the arithmetic and logic circuit. The arithmetic and logic operation circuit executes operations using these two inputs. The results are latched into the first and second accumulators, and the shift setting value of the shifter is set. When performing the above operations, due to the function of the auxiliary bus, 1
Arithmetic and logic operations can be executed by the arithmetic and logic circuits without occupying the main bus during instructions.

Further, the functions of the numerous auxiliary buses allow trigonometric function conversion and logarithmic conversion to be performed by accessing the data ROM without occupying the main bus, thus solving the problems of the prior art.

(Example) Examples of the present invention will be described in detail below.

FIG. 1 is a block diagram showing the configuration of a digital signal processing processor of this embodiment. This signal processing processor includes a sequence control section, a data RAM section, a data ROM section, an MPY section, an Al1 section, an input/output interface section, a data bus 31 common to each section, and a large number of auxiliary data buses. configured. The sequence section includes a stack 1 that outputs jump instructions, etc., and a program counter (PC) 2 that controls reading of the program memory 3.
, a program memory 3 that stores signal processing programs.
and a pipeline register 4 for matching processing instructions. The data RAM section has a three-sided data RAM, that is, a first data RAM 8, a second data RAM 7, and a third data RAM 10, and the memory read addresses of these data RAMs 8, 7, and 10 are set respectively under the control of the program. First to third data RAM address counters (MPO)5. (MPl)6. (MP2)
9, a data RAM selector 14, a data RAM input selector 15, and first and second temporary storage registers (TR) for temporarily saving the contents of the main bus 31F.
I) consists of 16 and (TR2) 17. The data ROM section is provided independently of the data RAMs 8, 7.10, stores fixed data, and stores the program and the third data RAM.
It consists of a data ROM 13 whose read address is set and whose contents are read by l0, a data ROM address counter (RP) 12 which controls reading of the single data ROM 13, and a data ROM address selector 11. MPY
The section includes a latch input selector 18 for selecting and inputting a multiplier for multiplication, an L latch input selector 20 for selecting and inputting a multiplicand, an MPY driver latch (19) for latching the multiplier, and an MPY driver latch (19) for latching the multiplicand.
21, and M to perform multiplication by the input multiplier and multiplicand
A shifter (MSFT) 23 that shifts the multiplication result of PY22 and MPY22, and M that latches the shift result.
It consists of a PY output latch (ML) 24.

The ALU section outputs data RAM and data ROM l? Power,
ALU 25 receives two inputs from the MPY output, the contents of the accumulator, and the contents of the main bus and performs calculations;
Flag register (FLAG IIEG) for detecting overflow of calculation results by monitoring 25 flags
26, and first and second accumulators (ACC
O) 27° (ACCI') 28 and a shifter () that shifts the contents of the first accumulator (ACCI) 2.7
ASFT) 29 and the first accumulator (ACCO)
The accumulator output selector 30 selects either the contents of the shifter (ASFT) 27 or the shifter (ASFT) 29 and supplies it as one input to the ALU 25. The input/output interface section has independently provided serial output registers (So 1).
34° (S02) 32, serial input register (S11
)35. (SI2) 33, parallel output register (OR
) 40, a parallel input register (IR) 41, serial output terminals 36, 38, serial input terminals 37, 39, and a parallel input/output port 42.

Immediate data from the program memory 3 and input data from the input/output interface section are transferred to the main bus 3.
1 is input. Data RAM 8.7.10 has three components, each having its own address counters 5 and 6.9. In this embodiment, the first and second data RA
M8.7 stores two variable data, and the third data RAM
l0 stores data ROM read control data.

The output of the first data RAM 8 passes through the data RAM output selector 14 to the latch input selector 18 and A of the MPY section.
It is input to the P side of the LU 25 and the main lot 31. Second
In addition to the route input to the main bus 31, the output of the data RAM 7 passes through the data RAM output selector 14 to the M
The PY section has a route that is input to the latch input selector 18 and the P side of the ALU 25, and the MPY section has a route that is input to the latch input selector 20 and the Q side of the ALU 25. The output of the third data RAM 10 is input to the data ROM address selector 11 and the main bus 31. The data ROM 13 has a one-sided configuration and has its own address counter (RP) 12 and address selector 11.

The input to the address selector 11 is the third data RAM1.
There are two routes: 0 output route and main bus 31 route.

The output of the data ROM 13 is input to the main bus 31, the latch input selector 20 of the MPY section, and the Q side of the ALU 25. The input to the Q side of ALU25 is main bus 3.
It also has one route.

The output of the ALU 25 is sent to the first and second accumulators (A
CCO)27. (ACC) 28 or both. First accumulator (ACCO) 27
The output of passes through the shifter (ASFT) 29 to the main bus 3.
1 and is input to the accumulator output selector 30.

The output of the second accumulator (ACC1) 28 is input to the main bus 31 and the accumulator output selector 30. The data selected by the accumulator output selector 30 is transferred to the latch input selector 18 and AL of the MPY section.
It is input to the P side of U25. Also, from the main bus 31, there is an output register (Sol) of the input/output interface section.
34. (SO2) 32° (OR) 40, each data RAM
Address counters 5, 6, 9, data RAM input selector 15, first and second temporary storage registers (TRI) 1
6° (TR2) 17 can also be input.

As described above, in this embodiment, there is a main bus 3 between each element.
In addition to 1, many auxiliary buses are connected, and each can operate independently.

Next, the operation of this embodiment will be explained in terms of multiplication and arithmetic and logic operations.

First, let's talk about multiplication. Here, it is assumed that the multiplier and multiplicand for multiplication are read from the first and second data RAMs 8.7. In the first step, the read addresses of the first and second data RAMs 8.7 are loaded into the RAM address counter 5.6. In the second stage, the contents of each address of the first and second data RAMs 8.7 are read out, and at the same time, the contents are outputted via the data RAM output selector 14, K latch input selector 18, and L latch input selector 20. , the multiplier and the multiplicand are latched in the latch 19 and the latch 21, and the MPY 22 and shifter 23 execute a multiplication and shift operation. In the third stage, the MPY output latch 24 latches the result of the multiplication and shift operation.

Note that in the above, the input of the multiplier and the multiplicand is from the first and second data RAM 8.7, but for example, the input of the multiplier and the multiplicand is
The output of the data RAM 7 and the data ROM 13 may be latched as the multiplicand. In this case, the control data stored in the third data RAM10 causes the data RO
Reading of M13 is performed. Of course, other connections are also possible.

Next, we will discuss arithmetic and logical operations. Here - as an example, one of the data on which an arithmetic and logic operation is to be performed is stored in the accumulator 27, and its shift value is transferred to the shifter 29,
0, and the other data is read out from the second data RAM 7.

In the first stage, the data RAM address counter 6 is loaded with the read address of the second data RAM 7. Second
At this stage, the address contents of the second data RAM 7 and the data converted from the accumulator 27 into shift data by the shifter 29 and passed through the accumulator output selector 30 are input to the ALU 25, and an arithmetic and logic operation is executed. In the third stage, it is latched into the accumulators 27 and 28, and the shift setting value of the shifter 29 is set.

It goes without saying that in this case as well, arithmetic and logical operations can be performed using other inputs to the ALU 25 than those mentioned above.

(Effects of the Invention) As described in detail above, according to the present invention, a large number of auxiliary buses are provided in addition to the main bus, which are used efficiently, so each function can be operated separately for one instruction. Become.

Therefore, it is possible to expect the effects of multiplication of two variable inputs, arithmetic and logical operations, shift control, and trigonometric function conversion and logarithmic function conversion by accessing the memory for reading without dedicating the main bus during one instruction. In addition, since the auxiliary bus from the accumulator output selector is connected to both the multiplication circuit section and the arithmetic logic circuit section, many operations can be performed without using the main bus. Since there are two auxiliary bus routes for inputting to the multiplication circuit section and the arithmetic logic operation circuit section, it is possible to execute variable doubling and squaring operations in one cycle time per instruction.

[Brief explanation of the drawing]

FIG. 1 is a block diagram showing the configuration of a digital signal processing processor according to the present invention, and FIG. 2 is a block diagram showing the configuration of a conventional digital signal processing processor. 2...Program counter 3-Program memory 5.6.9-...Data RAM address counter? , 8
．． 10--Data RAM 13--Data ROM 16.17--Temporary storage register 22--Multiplier (MPY) 23--Shifter 25--Arithmetic logic unit (ALU) 27.28-- Accumulator 29--Shifter 31--Main bus

Claims (1)

[Claims] A sequence control unit that performs program control for signal processing, and first and second data RAMs that store two-variable data.
, a third data RAM that stores data ROM control data, a data RAM input selector that selects inputs of the first and second data RAMs, and a data RAM address counter that sets the memory read address of each data RAM. a data RAM output selector for selecting outputs of the first and second data RAMs; and a data RAM output selector for selecting outputs of the first and second data RAMs;
a data RAM unit provided independently of the data RAM and having first and second temporary storage registers that temporarily store the contents of the main bus; , a data ROM which stores fixed data and whose read address is set and contents are read under the control of the sequence control unit and the third data RAM, and the output of the sequence control unit and the third data RAM via the main bus. Data R for selecting output
A data ROM section that has an OM selector and a data ROM address counter that controls reading of the data ROM; A multiplier circuit section that has a multiplication circuit that takes in multiplier and multiplicand inputs and executes multiplication; A multiplication circuit section that takes in two inputs and performs arithmetic and logic operations. an arithmetic and logic operation circuit to execute, and first and second accumulators that accumulate the operation results of the arithmetic and logic operation circuit in one or both;
an arithmetic logic operation circuit section having a shifter that shifts and controls the output of the first accumulator; and an accumulator output selector that selects the output of the shifter and the second accumulator; It is equipped with an input/output interface section that sends and receives signals, and a main bus that is a data bus that commonly connects the blocks in each of the above sections, and between the components within the blocks, as well as between the components within the block and the components of other blocks. , a large number of auxiliary buses are provided for connection with other blocks and the main bus, and data RAM output, data ROM output, and accumulator contents are input to the multiplication circuit, and data RAM output, data ROM output, multiplication circuit output,
A processor for digital signal processing, characterized in that the contents of an accumulator and the contents of a main bus are input to the arithmetic and logic operation circuit.