JPH01311319A - Bus control circuit - Google Patents

Abstract

PURPOSE:To reduce an increase in the size of a circuit due to an increase in the number of buses for operation data and to optionally control the flow of operation data by selecting a combination of a connection between a memory data sending circuit and a data bus, and one of memory data fetching circuits. CONSTITUTION:Memories 118-121 send data to all of buses 100-103 through the memory data sending circuits 114-117. In this case, a data control circuit 104 sends control signals to control lines 122-125, 126-131. The control signals are stored in a program storing circuit as a pair of data. Thus, data flow between the circuits 114-117 and the memory data fetching circuits 105-110 can be controlled.

Description

DETAILED DESCRIPTION OF THE INVENTION (Field of Industrial Application) The present invention relates to a bus control circuit, and more particularly to a bus control circuit that controls the flow of data to a bus in a digital signal processor.

(Prior Art) Digital signal processing processors (hereinafter sometimes simply referred to as processors) of various structures have been used in applications such as synthetic speech and digital filters. The performance of such a processor is usually evaluated based on how fast it can perform calculations on numerical data.

FIG. 3 is an explanatory diagram of numerical data and the flow of calculations in this conventional German processor. In this figure, 30
1 is X memo 1 consisting of RAM and ROM, 302 is RA
This is a Y memory consisting of M and ROM. Numerical data used for calculations are appropriately distributed and stored in these memories. 303 is an address ALU, and X memory 301. The addresses of the numerical data stored in the Y memory 302 are managed. 304 is a data ALU that performs necessary calculations based on numerical data. 305 and 306 are respectively X address buses.

Y address bus, 307.308.309.310.3
11.312 are data buses.

The numerical data and calculation flow in FIG. 3 will be explained next.

First, the X memory 301. The numerical data stored in the Y memory 302 is transferred to the bus 307.308.309.310.
．． 311 and 312 to the data ALU 304. At this time, the address of the data read from the X memory 301 is controlled by the address ALU 303 via the X address bus 305. Similarly, regarding the Y memory 302, the address ALU 303 and the Y address bus 3
Controlled by 06. Then, the numerical data is subjected to calculations in the data ALU 304, and the calculation results (hereinafter sometimes referred to as calculation data) are written to the X memory 301 or the Y memory 302 by retracing the above-mentioned path.

FIG. 4 is a configuration block diagram showing an example of the data ALU 304 in FIG.
56000 manual). In this figure, 400
゜401, 402.403 C registers X, Y, A respectively
, B, 404 is a multiplication/accumulation/logic unit, 405 is an accumulator/shifter, 406 is a multiplier/control recorder, 407 is a shifter/limiter, 408 is a bit manipulation unit, 409 is an X data bus, 4
10 is a Y data bus, 411 is a calculated data data bus, 412 is a data line, 413.414.415.416
is the local data bus. In addition, the X data bus 40
9 is Fig. 3 (7) Lotus 311 D, Y data bus 41'
.

is connected to bus 312 in FIG.

In FIG. 4, an X data bus 409, a Y data bus 4
The data on 10 is in registers X, Y, A, B4O0-4.
03. And register X.

The outputs of Y, A, B 400 to 403 are connected to data line 4.
12, is input to the multiply-accumulate logic unit 404 via local data buses 413.414.415. In this case, registers A, B, X, Y 400-40
3 (7) Husband/? (7) The output can be connected to either of the two local data buses 415. That is, in the circuit of FIG. 3, the data bus 309 and the X memory 3
01 and data ALU 304's X data bus 31
1 (409), data bus 310, Y memory 302, and Y data bus 312 (409) of data ALU 304.
10) are fixedly connected to each other, so X, data, Y
It is not possible to flow the data to the data bus 312 or to flow the Y data to the X data bus (data exchange) before inputting the X data and Y data to the data ALU 304. The local data bus 415 and a local data bus 416 are provided to enable data exchange within the data ALU 304. Enabling data exchange in this way is advantageous in that the data storage location can be set relatively freely when creating a program, making it easier to create a program.

(Problem to be Solved by the Invention) However, in the conventional processor with the above configuration, there are two buses for calculation data, the X data bus 309 and the Y data bus 310, so two local data buses in the data ALU 304 are used. 415, data can be exchanged, but in order to increase the processing power of the processor, there are three additional buses for calculation data.

If the number of local data buses is increased to four, data on the buses cannot be exchanged freely unless the number of local data buses within the data ALU 304 is also increased. When the number of local data buses is increased, the number of program steps increases and the number of instruction control bits must be increased in order to freely flow calculation data on the increased buses and local data buses. There was a problem in that the data exchange made it more difficult to create programs.

The present invention solves the problem that, according to the conventional data exchange method in processors, when the number of arithmetic data buses increases, it becomes difficult to create a program, and also reduces the increase in circuit scale due to an increase in the number of arithmetic data buses. It is an object of the present invention to provide a digital signal processing processor with high processing ability by making it possible to arbitrarily control the flow of calculation data.

(Means for Solving the Problems) The present invention provides a bus control circuit for a digital signal processing processor having a plurality of arithmetic units, a plurality of memories, and a plurality of buses.
(]) a memory data sending circuit connected to the memory and connectable to any of the buses; and a memory data importing circuit fixedly connecting the bus and the arithmetic unit;
a bus control circuit including one data control circuit that controls a combination of the memory data sending circuit and the memory data capturing circuit; (2) a calculated data capturing circuit that provides a fixed connection between the memory and the bus; A bus control comprising a calculated data sending circuit connected to an arithmetic unit and connectable to any of the buses, and one data control circuit that controls a combination of the calculated data sending path and the calculated data acquisition circuit. (3) The bus control circuit (1) and (2).

(Function) The bus control circuit of the present invention (hereinafter sometimes referred to as the circuit of the present invention) (1), (2), or (3) may be used in any of the data buses. The memory data or calculated data can be sent to any data bus.

Further, the memory data acquisition circuit and the calculated data acquisition circuit are fixedly connected to one of the data buses, and acquire memory data or calculation data through a specific data bus.

The data control circuit used in the circuit of the present invention is selected by combining a memory data sending circuit, a data bus connection, and a memory data acquisition circuit in the bus control circuit (1), and in the bus control circuit (2). has a function of selecting a combination of a calculated data sending circuit, a data bus connection, and a calculated data importing circuit, and controlling the data route.

The circuit of the present invention, which is a combination of these circuits, is
Despite the relatively simple configuration, data can be freely exchanged under the control of the data control circuit.

However, when numerical operations are performed by a processor, data exchange generally does not need to be possible for all combinations between memory and arithmetic units. This is because the data transmission side (source) and the data acquisition side (data acquisition side) are usually connected via a data bus.
This is because the data control circuit has a strong correlation in processing and is often linked, so the data control circuit can be operated based on this correlation so that only necessary data exchange can be performed. In this sense, according to the circuit of the present invention, the degree of freedom of data exchange can be easily increased as well as decreased, and by taking the above-mentioned correlation into consideration, a processor with the minimum degree of freedom necessary can be constructed. becomes possible. Therefore, the number of program steps and number of instruction bits for bus control can be reduced. Furthermore, since the connection between the component circuits of the circuit of the present invention and the data bus can be easily patterned, the circuit of the present invention can be widely and flexibly applied to bus configurations depending on the purpose of the processor.

Here, the correlation between the sending side and the receiving side described above will be briefly explained. Normally, in numerical calculations, a series of multiplications, additions, subtractions, etc. are performed all at once in software, so for the convenience of data processing, numerical data added to multiplication, numerical data added to addition/subtraction, etc. are often grouped together and stored in separate memories. As a result, during calculation, the data path between the data sending side and the data receiving side (computing unit) is dedicated to some extent depending on the type of data. This means that there is a strong correlation between data processing on the sending and receiving sides.

(Example) Embodiments of the present invention will be described below with reference to the drawings.

FIG. 1 is a configuration block diagram showing an embodiment of a bus control circuit (1) of the present invention. In this figure, 100~
103 is a data bus, and in this embodiment, four data buses are used. 104 is a data control circuit, 105
-110 are memory data import circuits, 111-113 are all arithmetic units, 111 and 112 are multipliers, 11
3 is an adder/subtracter. 114 to 117 are memory data sending circuits, and 118 to 121 are memories for storing numerical data. 122 to +25 are control lines for selecting connections between the memory data sending circuits 114 to 117 and data buses 100 to 103, and 126 to 131 are control lines for controlling data loading to the memory data loading circuits 105 to 110. , control lines 112-125 and control lines 126-
131 are controlled in combination by the data control circuit 104. Further, 132 is a program storage circuit for controlling the data control circuit 104, and 133 is its control line.

As shown in FIG. 1, in this embodiment, the memory data acquisition circuits 105 to 110 are connected to data buses 100 to 1
03, and the multiplier 11
1 and 112, and the adder/subtractor 113 are also fixedly connected. The memory data acquisition circuits 105 to 110 are
Since it is only necessary to control two states: whether or not to take in the data on the data buses 100 to 103, the control line 12
6 to 131 are each 1 bit.

Further, the memory data sending circuits 114 to 117 are arranged to be connectable to any of the four data buses 100 to 103, and are fixedly connected to the memories 118 to 121, respectively. Therefore, the memories 118 to +21 are connected to the data bus 1 via the memory data sending circuits 114 to 117.
It is possible to send data to any of the buses 00 to 103. In this case, it is the data control circuit 104 and the control lines 122 to 125 that control which data bus the data is sent to. Therefore, control line 122
~+25 are each 4 bits in this embodiment.

FIG. 5 is a circuit diagram showing an example of the memory data sending circuit of FIG. 1. In this figure, buffers 500 to 503 select connections between the memory data sending circuit 114 and the data buses 100 to 103, and are controlled by the 4-bit control line 122 via a control line 504. 50
Reference numeral 5 denotes a data line that fixedly connects the memory data sending circuit 114 and the memory 118.

Next, bus control by the bus control circuit (1) shown in FIG. 1 will be explained.

As described above, the data control circuit 104 operates on the control line 12.
A total of 22 bits of control signals from control lines 2 to 125 and control lines 126 to 131 are sent out. Examples are shown in Table 1 below.

(Left below) This 22-bit control signal is stored, for example, in the program storage circuit 134 shown in FIG. 1 as a set of data. In this way, by specifying an address, the flow of data between the memory data sending circuits 114 to 117 and the memory data receiving circuits 105 to 110 can be easily controlled by simply specifying this address. and,
Even if the number of data buses is increased, data can be freely flowed between the memory and the arithmetic unit without increasing the number of local buses in the arithmetic unit such as the data ALU.

By the way, if the bus is controlled by the method described above, the data flow can be freely selected, but it seems that the number of 22-bit data sets to be stored in the program storage circuit 134 becomes enormous. However, in reality, as mentioned in the operation section above, numerical operations processed by a digital signal processor have a strong correlation between memory and arithmetic units, so memory data sending circuits 114 to 117 and memory data importing circuits 114 to 117 Since the circuits 105 to 110 often need to be interlocked, the number of data sets to be prepared is limited. Therefore, the data control circuit 104 only needs to generate the necessary control signal patterns, and the control line 133 only needs to instruct one of the limited patterns.

Next, the above correlation will be explained using a specific example.

Now, consider the case of calculating (x" + y - z).Then, the numerical data of X is stored in memory (1) 118, the numerical data of y is stored in memory (2) 119, and the numerical data of Z is stored in memory (3). ) 120, and the calculation results of x2 (calculation data) and the calculation data of y'z are stored in the memory (4
) 121. During arithmetic processing, the data control circuit 104 receives the control signal stored at address O in Table 1. At this time, the data in the memory (1) 118 is input to the multiplier Ill via the memory data acquisition circuits 105 and 106 to calculate x2, and the calculated data is stored in the memory (4) 121. Next, the control signal stored at address l is received. At this time, memory (
The data stored in the memory (2) 119 and the memory (3) 120 is input to the multiplier 112 via the memory data acquisition circuits 107 and 108, respectively, to calculate y-z, and the calculated data is stored in the memory (4H21). Then, it receives the control signal stored in address 2. At this time, the memory (
4) The data stored in +21 is manually input to the adder/subtractor 113 via memory data acquisition circuits 109 and 110, respectively, and x2+y-z is calculated. In this way, the arithmetic processing can be simplified by creating a correlation between the numerical data in the memory and the processing in the arithmetic unit according to the content of the arithmetic operation. Although a simple calculation example is used here, the same holds true even if the calculation contents become complex.

Additionally, if the content (program) to be processed changes, the necessary control signals may also change, but in such a case, the data control circuit 104 can be configured with a ROM, etc., and the control signal can be changed by exchanging the data control circuit 104 in pairs with the program. Programs can be created without being bound by possible patterns, and highly flexible processors can be constructed. Since the circuit of the present invention has a configuration that can be easily patterned, it is suitable for constructing a highly versatile and highly flexible processor.

FIG. 2 is a block diagram showing an embodiment of the bus control circuit (2) of the present invention. In this figure, 200-2
02 are all arithmetic units, 200 and 201 are multipliers,
202 is an adder/subtracter. 203 to 206 are memories that store numerical data. 207 to 209 are calculation data sending circuits, and 210 to 213 are calculation data acquisition circuits. 214 to 217 are data buses, and in this embodiment, four data buses are used. 218-22
0 is calculated data sending circuits 207 to 209 and data bus 2
Control lines for selecting connections between 14 and 217, 221-2
Reference numeral 24 denotes a control line for controlling the acquisition of data into the calculation data acquisition circuits 210 to 213. A data control circuit 225 controls the control lines 218 to 220 and the control lines 221 to 224 in combination. Further, 227 is a program storage circuit for controlling the data control circuit 225;
26 is its control line.

This embodiment is a case of data transfer from an arithmetic unit to a memory as shown in FIG. Calculation data acquisition circuit 210~
213 are all fixedly connected to one of the data buses 214 to 2+7, and also have memories 203 to 206, respectively.
Both are fixedly connected. In addition, the calculation data sending circuit 2
07 to 209 are arranged to be connectable to any of the four data buses 214 to 217, and are fixedly connected to the multiplier 2001, the multiplier 201, and the adder/subtractor 202, respectively. Therefore, these arithmetic units 200 to 202 are connected to the data bus 214 via calculated data sending circuits 207 to 209.
It is possible to send data to any of the buses .

Bus control in the bus control circuit (2) of the present invention can be performed in the same manner as in the bus control circuit (1) already described. In this case, it is useful to consider the correlation between the arithmetic unit and memory, and it goes without saying that this simplifies bus control.

Further, it is preferable to combine the bus control circuits (1) and (2) of the present invention because the effects obtained when each is used alone can be synergistically enhanced. For example, this is effective when the control pattern can be halved and the number of control bits can be halved in each of the data control circuits 104 and 225.

By combining in this way, program creation can be made even more flexible. Note that in this case, the data control circuit, program storage circuit, etc. can be configured as one unit.

(Effects of the Invention) As described above in detail, the present invention provides: ■ A memory data or calculated data sending circuit that can flow data from a memory or an arithmetic unit to an arbitrary data bus; ■ A data bus and an arithmetic unit, or Memory data or calculated data fixedly connected to memory (hereinafter simply referred to as data)
The provision of an acquisition circuit eliminates the need for local buffers in the arithmetic unit, which were conventionally used in processors. ■The provision of a bus control circuit that controls the data transmission circuit and data acquisition circuit in conjunction with each other enables data transmission. The program cost for controlling the circuit and data acquisition circuit can be reduced.

Therefore, according to the present invention, the bus configuration can be simplified and bus control can be facilitated. In particular, in the bus configuration, the present invention provides
This is useful when there is a correlation between the data sending and receiving sides.

Further, since the present invention is versatile, it can be widely applied regardless of the type of processor.

[Brief explanation of the drawing]

FIG. 1 is a configuration block diagram showing an embodiment of the bus control circuit (1) of the present invention, and FIG. 2 is the bus control circuit (2) of the present invention.
3 is an explanatory diagram of the flow of numerical data and calculations in a conventional processor. FIG. 4 is a block diagram showing an example of the data ALU 304 in FIG. 3. FIG. 5 is a circuit diagram showing an example of the memory data sending circuit in FIG. 1. 100~103.214~217...Data Busumi 1
05-110...Memory data acquisition circuit, 114-1
17...Memory data sending circuit, 207-209...
- Calculated data sending circuit, 210-213... Calculated data acquisition circuit, 104, 225... Data control circuit, 1
22-131.218-224... control line, 132,
227...Program storage circuit. Patent applicant: Oki Electric Industry Co., Ltd. Procedural Ner'lT official document (spontaneous) February 6, 1989

Claims (1)

[Claims] 1. A bus control circuit for a digital signal processor having a plurality of arithmetic units, a plurality of memories, and a plurality of buses, the memory data sending circuit being connected to the memory and connectable to any of the buses. A bus control circuit comprising: a memory data acquisition circuit that fixedly connects the bus and the arithmetic unit; and one data control circuit that controls a combination of the memory data transmission circuit and the memory data acquisition circuit. 2. A bus control circuit for a digital signal processing processor having a plurality of arithmetic units, a plurality of memories, and a plurality of buses, the calculation data acquisition circuit having a fixed connection between the memory and the bus; A bus control circuit comprising a calculated data sending circuit that is connectable to both, and one data control circuit that controls the calculated data sending circuit and the calculated data capturing circuit in combination. 3. A bus control circuit for a digital signal processing processor having a plurality of arithmetic units, a plurality of memories, and a plurality of buses, the memory data sending circuit being connected to the memory and being connectable to any of the buses; A memory data acquisition circuit that provides a fixed connection between arithmetic units; a calculated data acquisition circuit that provides a fixed connection between the memory and the bus; and a calculated data that is connected to the arithmetic unit and is connectable to any of the buses. A bus control circuit comprising a transmission circuit, a data control circuit that controls a combination of the memory data transmission circuit, the memory data acquisition circuit, and the calculated data transmission circuit and the calculated data acquisition circuit, respectively.