JPS59186070A - High speed signal processor - Google Patents

Abstract

PURPOSE:To realize a high speed signal processor by applying the complex sum of product operation obtaining one result in one clock cycle to a high speed Fourier transformation processor. CONSTITUTION:The high speed processing is attained by repeating the butterfly operation given by a specific expression A rotation factor W read by a constant storage memory is inputted to a multiplier 14 via a K register 11. On the other hand, after the real part of a data input B is stored in a J2 register 13 and the imaginary part is stored in a J1 register 12, any of them is selected and inputted to the multiplier 14. The result of multiplication is inputted alternately to an operating circuit 17 via a register M15 or an N16. The circuit 17 operates complex sum of product of BXW in the specific Equation and stores the result to a P register 18. On the other hand, the real part of an input A is inputted to an L1 and the imaginary part is inputted to an L2 register, and one output of them is inputted to an operating circuit 21 together with an output of the P register 18 through registers L1', L2'. The circuit 21 adds the input A and the BXW and the final result is inputted to a register Q22.

Description

DETAILED DESCRIPTION OF THE INVENTION The present invention relates to a high-speed signal processing device that digitally performs a product-sum operation, a so-called butterfly operation.

<Background> Due to recent advances in signal processing technology, there is a growing movement to shift from traditional analog systems to digital systems. The equation (1) is the basis of this digital signal processing algorithm. -A'=A+B-W
(1) Here, A, B, W, and A' are complex data. Many parts of current digital signal processing algorithms, such as fast Fourier transform, digital filtering, and convolution operations, are
1) It can be expressed as a combination of equations. Therefore, how to execute this calculation at high speed is a key technical point for speeding up digital signal processing. A number of architectures have been proposed to speed up the processing (pipeline processing, parallel processing, etc.), but in the past, one method was to perform one multiplication in two clock cycles, or to A method such as operating two multipliers in parallel was used as a two-system data bus configuration.Also, adding circuits and data buses were repeatedly used multiplexed, but such data bus multiplexing was not implemented until now. If you take this into account, it has the drawback of making the system significantly more complex.

<Objective of the Invention> The object of the invention is to perform one multiplication in one clock cycle, and transfer one unit of butterfly operation results consisting of four complex numbers to one set of data buses in four clock cycles. It is an object of the present invention to provide a high-speed signal processing device that outputs one complex product-sum operation result in two clock cycles.

<Example> A detailed explanation will be given below according to the drawings.

FIG. 1 shows an example of a fast Fourier transform process for the present invention. In the case of fast Fourier transform, it is achieved by repeating the butterfly operation given by equation (2) below.

+ 1m (B) -Re (w) ) ・・・・・・・・・・・・・・・・・・・・・・ (2) Here, A,
B is the input data at each butterfly calculation stage, W
is the twiddle factor constant.

The twiddle factor W read out from a constant storage memory (not shown) is input to a multiplier 14 via a register 11.

On the other hand, the real part of the data input B is once stored in the J2 register 13 and the imaginary part in the Jl register 12, and then one of them is selected by the selection control line 26 and inputted to the multiplier 14. The multiplication result of the multiplier 14 is stored in the M to N registers 15.
, 16, and are alternately input to the arithmetic circuit 17 from these registers 15, 16.

The arithmetic circuit 17 performs addition and subtraction of the outputs of the registers 15 and 16, and calculates the operation in parentheses in equation (2), that is, B
The complex multiplication result of input register Ri,
, and the output of one of them is input to the arithmetic circuit 21 along with the output of the P register 18 through the Ll+L'2 register provided to take timing with the delay caused by Ri2. The arithmetic circuit 21 performs addition and subtraction between input A and BXW, and the final result is input to the Q register 22.

When an arithmetic circuit is constituted by hardware, it is important to prevent overflow and underflow, but this product-accumulation signal processing device prevents both by performing block floating point arithmetic. Since the absolute value of the twiddle factor W is equal to 1 by definition, if the input B is an n-bit word length, the multiplication result only needs to be n bits. Furthermore, since the addition and subtraction in the arithmetic circuit 17 is also part of the BXW multiplication, its output never overflows n bits. Therefore, the arithmetic circuit 17 may have an n-bit configuration. However, since the arithmetic circuit 21 performs addition and subtraction of two independent n-bit numbers, there is a possibility of overflow. Therefore, the arithmetic circuit 21 has an (n+1) bit configuration in which the input bits are expanded to (n+1) bits as shown in FIG. 2 to prevent overflow. The figure shows an example in which 8 bits are expanded to 9 bits.

In addition, a scaling control 828 (n+1) provided by an external automatic scaling controller (not shown) is provided.
Of the bit outputs, either the upper n bits or the lower n bits are selected by the R register 23 in FIG. 1 and output as a complex product-sum output. The control line 28 is arranged so that the upper n bits are selected when the maximum absolute value of the input data exceeds 1/2 of the number that can be expressed by n bits.

Here, when the upper n bits are selected, d-, the LS of the data
The direction of the quantization error generated by deleting B (lowest pick l-) is reversed in positive and negative values. Therefore, when the data value is positive, the LSB is deleted by the rounding implement circuit 24.
A rounding correction is performed by arranging the directions of the errors. When the data from the count circuit 22 is negative, the least significant bit is simply removed.

A detailed diagram of the rounding operation circuit 24 is shown in FIG. That is, if the data is positive, the most significant second bit (MSB) is 0,
It is inverted by an inverter 51 and given to an AND circuit 52; if the number is odd, the least significant bit (LSB) is 1 and the output of the AND circuit 52 is 1;
When the LSB is 0, the output of the AND circuit 52 is 0, and the addition circuit 30 performs O discarding.

If the input data is positive and has the maximum value, this is detected by the AND circuit 53 and one person is prohibited. If the input data is negative, the MSB is 1 and the output of the inverter 51 is O, and the adder circuit 30 adds 0.

Note that all data transfer and arithmetic operations are controlled by microinstructions supplied from a control unit (not shown) so as to perform pipeline operations.

FIG. 4 shows an operation timing chart of the butterfly arithmetic circuit using the device shown in FIG. J at the 1st clock
Load the imaginary part Im(B) of data B into the register 12,
At the second clock, the real number s Re (B ) of data B is
2 registers 13, each of these data is held for 4 clocks, and the imaginary part Tm(W) of the twiddle factor is set to the 1st. The third clock inputs these signals into the respective registers 11, and the second . At the fourth clock, the real part R8(W) of the twiddle factor is transferred to the register Ril at the second clock. At the 4th clock, they are respectively fetched into the register 11 and transferred to the register R12, and the result is ``y 3'', and at the 4th, 5th and 6th clocks, the ride result ■-Im(B) x 1.
m(w), ■-Re(B) x I field (W), ■-Re
(B)xlm(w), and ■-Im(B)xRe(
W), put the ■ into the M register 15, the ■ into the N register 16, and put the ■ into the M register 15 and the ■ into the N register 1.
6 respectively. Fifth. ■＝■− at the 6th cross
Put the result of ① into P register 18, @7. At the 8th clock, put the result of ■巳■+■ into P register】8. On the other hand, at the third and fourth clocks, the real part R8(A) and imaginary part 1m(A) of data A are stored in the L] register 19 and L2 register 20, respectively, and are held for 4 clocks each. ), Im(
The 4th clock is one clock behind A). At the fifth clock, the contents of the Ll, I;z registers and P register 18 are transferred to the French register and t2 register, and the sixth. 7th. ■''-■, ■=■, ■+■ and ■-■ are obtained in the Q register 22 at the eighth and ninth clocks, respectively. In other words(
2) Each value Re(A'), Re(B') of the formula.

1m(A') and Irn(B') are obtained in these 4 clocks.

In this way, the multiplier 14 outputs one multiplication result for each clock cycle, resulting in a stock volatility of approximately 100.
The four multiplications required for the exposure no-toughfly operation q0 are accomplished in four clocks, and one complex no-toughfly operation result can be obtained every lock cycle for each no-ζ-ebrine operation result. . In this case, the selector 25 is the R register 23
output is selected.

Although the computation flow on Ju allows the output of complex summation computations such as Nokutafly computation, it is difficult to obtain the output of complex summation computations such as Nokutafly computations. In some cases, such as multiplication, only a complex multiplication IL-J is required. In such a case, the complex multiplication result can be easily obtained by providing a window function or a convolution function instead of the twiddle factor W and selecting the output of the P register 18 with the selector 25.

FIG. 5 shows an embodiment of a fast Fourier transform processor in which 7C Toughfly calculation stages are connected in cascade using the device for performing the product-sum operation shown in FIG. Memo' J M+ +
M237 is data input/output memory, memo') Ma38
is a constant storage memory. If the number of data is N, m = log2 N...
. . . (3) A butterfly calculation is required for the m1-fixed stage, but according to this example, m stages 34 are connected in cascade, and a read address 32 common to all stages is used. By providing a write address 33 and a write address 33 to the name stage 34 and performing bit swapping of the addresses at jumper terminals 39 and 40 in each stage 34, a fast Fourier transform is performed while the input data passes through the processor. The structure is as follows.

The constant storage memory M3 is accessed by the read address, but the jumper terminal 39 in the first stage is used to access the constant storage memory M3.
The bit exchange is performed as follows. That is,
The upper (i-1) bits of the address line given to the memory contain the lower two bits of the address.
Connect the bits in the reverse order of upper and lower bits, give all zeros to the lower (m-i) bits, and the total is (i-1) + (m-i)-m = 1... Old...
Apply the address line (4) to the memory M3. Number of data N
Table 1 shows an example of address exchange by this bit exchange in the case of =1024 and m=10.

Another input/output memo! Regarding J Ms + M2, when one memory is in the read state and data is being transferred to the product-sum calculation circuit, the other memory is always in the write state and writes the product-sum calculation result of the previous stage. , also 1
It is controlled by the control unit 31 so that the state is exchanged for each frame. The m-bit read address is given as is to the memory in the read state, but the m-bit store read address stored in the memory in the 1-write state is set to its lower order by the jumper terminal 40 in the first stage. The i bit is cyclically shifted by 1 bit in the upper direction and connected.Bit reversal is also performed for the first stage and the output buffer memory 35.Address 7 due to the focus exchange in the case of m-10 Examples are shown in Table 2.

By executing address conversion as described above, the order of butterfly calculations in each stage is changed, and butterfly calculations are always performed between data stored in adjacent addresses. In Figure 6, N=16. An example of the relationship between the input data and the combination data of the butterfly operation at each stage when m=4 is shown.

With this explanation, it is possible to obtain one complex product-sum operation result in one clock cycle, so for example, when applied to a fast Fourier transform processor, N = 1024 points of complex fast Fourier transform can be piped in 2054 clocks. I was able to do it in line.

Since one clock cycle operates at 100 n5ec and the calculation time is 205 μsec, real-time frequency analysis of up to 2.5 MHz as a Nerquist frequency is possible. - The operation word length in hardware is unified to (n+1) bits, for example,
If there is a risk of oats (-flow) due to calculation,
n-bit data was used for calculations. However, in the example shown in FIG. 1, the arithmetic circuit 21°Q register 22. R register 23. Instead of configuring only the rounding operation circuit 24 with an (n+1) bit word length and the others with an n-bit word length, most of the device has an n-bit configuration and only a part has an (n+1) bit word length.
) bit configuration, it is possible to reduce the size of the node as a whole, and furthermore, all operations are performed using n-bit data in the stage before the arithmetic circuit 21, so that the entire data word length of the device can be reduced. The more you can use it, the more accurate calculations you can perform. -1 Since the multiplier 14 occupies a configurable part of the hardware in this device, in the past, everything was configured as n-bit word length hardware, and ('n-1) bit data was It is now possible to perform calculations on n-bit data using almost the same hardware as previously.

[Brief explanation of the drawing]

FIG. 1 is a block diagram showing an example of a high-speed signal processing device according to the present invention, FIG. 2 is a diagram showing data selection in the R register 23 in FIG. 1, and FIG. 3 is a rounding operation circuit in FIG. 1. 2
Logic circuit diagram showing the side of 4, FIG. 4 is a time chart showing the operation example of FIG. 1, and FIG. 5 is an FFT to which this invention is applied.
FIG. 6 is a block diagram showing an example of a processor, and is a diagram showing the relationship between data at each stage in FIG. 11: Constant register, 12, 13: Multiplication register, 1
4: Multiplier, 15, 16; Multiply value register, 17
, 21: Arithmetic circuit, 18: Arithmetic register, 19, 2
0: Addition/subtraction register. Patent Applicant: Asahi Kasei Industries Co., Ltd. Agent Takashi Kusano

Claims (1)

[Claims] (1) Constant register α theory and two multiplication registers (1
2, 13), a multiplier α◆ that multiplies the output of these two multiplication registers by the output of the constant register, and the multiplication result between the real parts of the multiplier α◆, or the multiplication between the real part and the imaginary part. two multiplication value registers (15, 16) into which the result and the multiplication result between the imaginary parts or the multiplication result between the real number part and the imaginary part are respectively input; 1 arithmetic circuit α power, an arithmetic register (b) into which the arithmetic results of the first arithmetic circuit are input, and two addition/subtraction registers (b) into which each of the real part and imaginary part of the second human power data is input. 19, 20), and a second arithmetic circuit (gl) that performs IIN-order addition and subtraction of the output of the arithmetic register α with the output of the two addition/subtraction registers, and the product of the constant and the first human data. A high-speed signal processing device that obtains four pieces of data including a real part and an imaginary part of the sum and difference between the data and the second human data.